Patents by Inventor Takuya Konno

Takuya Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210010848
    Abstract: A first arithmetic circuit computes a propagation velocity of an ultrasonic wave based on a first time difference between an output timing, at which an ultrasonic element outputs an ultrasonic wave, and a reference timing, at which a comparator circuit outputs a detection signal on reflection off a distal end of a reference pipe, and a length of the reference pipe. A period circuit sets a propagation path detection period to detect a liquid level timing, at which the comparator circuit outputs the detection signal on reflection off the liquid level, based on a longest and shortest propagation path lengths and the propagation velocity. A second arithmetic circuit computes the length of the propagation path based on a second time difference, which is between the liquid level timing and the output timing during the propagation path detection period, and the propagation velocity.
    Type: Application
    Filed: July 6, 2020
    Publication date: January 14, 2021
    Inventors: Kyoko KUROKAWA, Takuya KOIZUMI, Akihiro KONNO, Hironori IWAMIYA
  • Publication number: 20210010847
    Abstract: An ultrasonic element generates an ultrasonic wave and converts an input ultrasonic wave into an electric signal. A transmission circuit outputs a drive signal to the ultrasonic element. A comparator circuit outputs a first detection signal when the electric signal becomes larger than a threshold value and outputs a second detection signal when the electric signal becomes smaller than the threshold value. An arithmetic circuit computes a distance of a propagation path of the ultrasonic wave based on a time difference between an output timing, at which the ultrasonic element outputs of the ultrasonic wave, and a liquid level timing, at which the comparator circuit outputs the first detection signal, and based on a propagation speed of the ultrasonic wave. A storage unit stores a time difference between the first detection signal and the second detection signal. The transmission circuit increases the drive signal, as the time difference decreases.
    Type: Application
    Filed: July 6, 2020
    Publication date: January 14, 2021
    Inventors: Akihiro KONNO, Hironori IWAMIYA, Takuya KOIZUMI
  • Patent number: 10756047
    Abstract: The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 25, 2020
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventor: Takuya Konno
  • Publication number: 20200256985
    Abstract: A liquid level detector has an ultrasonic sensor connected thereto by two signal lines. When a drive signal is output from a drive circuit, the drive signal is output via an impedance matching circuit, thereby transmission and reception signals on the signal lines flow as complementary level signals. A receiver circuit obtains an amplified signal by amplifying the transmission and reception signals with a differential amplifier circuit, and by cutting a same phase noise signal.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Inventors: Takuya KOIZUMI, Hironori IWAMIYA, Akihiro KONNO
  • Publication number: 20200227480
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya KONNO
  • Publication number: 20200132144
    Abstract: A radially biasing portion (19) of a pad spring (14) includes a first extending portion (19A) extending from a lower surface plate (18B) of a guide plate portion (18) outwardly in a disc axial direction, a curled portion (19B) folded on a distal end side of the first extending portion, and a second extending portion (19C) extending from the curled portion in a direction approaching a disc (1), the second extending portion with which an ear portion (11A) of a friction pad (10) comes into contact. A contact portion (20) extends from the second extending portion of the radially biasing portion (19) toward a middle of the friction pad in a disc rotational direction of the friction pad. The contact portion comes into surface contact with a contacted surface (11B) as a lateral surface of the friction pad (backing plate 11) in the disc rotational direction.
    Type: Application
    Filed: May 17, 2018
    Publication date: April 30, 2020
    Inventors: Takuya KONNO, Shigeru HAYASHI
  • Patent number: 10615226
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: April 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Konno
  • Publication number: 20190393825
    Abstract: A failure diagnosis method for an inverter circuit, which easily performs failure diagnosis of a FET of the inverter circuit without delay includes comparing a motor terminal voltage corresponding to each phase of the inverter circuit including semiconductor switching devices (FETs) to drive a motor, with a threshold voltage by comparators as voltage comparison circuitry. At this time, the threshold voltage is changed according to a high-side FET and a low-side FET on which failure diagnosis is to be performed. Subsequently, by a digital output from the comparator, whether there is a short circuit of each FET of the motor terminal voltage is determined.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 26, 2019
    Inventors: Osamu MAESHIMA, Hajime NAKANE, Junichi KONNO, Takuya YOKOZUKA, Shunjiro OSANAI, Takafumi UMEMOTO
  • Publication number: 20190296044
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body and a columnar portion. The columnar portion is provided inside the stacked body and includes a semiconductor portion extending in a first direction. The columnar portion has widths having mutually-different sizes in a second direction perpendicular to the first direction. The widths include first and second widths. The first width is a width of the columnar portion positioned inside a first electrode film of lowermost layer of the electrode films. The first width is substantially the same width at positions in the first direction of the columnar portion. The second width is a width of the columnar portion positioned inside a second electrode film of the electrode films. The second width is substantially the same width at positions in the first direction of the columnar portion. The first width is smaller than the second width.
    Type: Application
    Filed: September 12, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazunori HARADA, Takuya KONNO, Daisuke HAGISHIMA
  • Publication number: 20190259813
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya KONNO
  • Patent number: 10325957
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Konno
  • Publication number: 20190035852
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya KONNO
  • Patent number: 10115771
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Konno
  • Publication number: 20180102341
    Abstract: The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.
    Type: Application
    Filed: September 19, 2017
    Publication date: April 12, 2018
    Inventor: Takuya Konno
  • Publication number: 20180047786
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya Konno
  • Patent number: 9842990
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marina Yamaguchi, Shosuke Fujii, Masumi Saitoh, Hiromichi Kuriyama, Takuya Konno
  • Patent number: 9812502
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 7, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Konno
  • Publication number: 20170271584
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.
    Type: Application
    Filed: December 21, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Marina YAMAGUCHI, Shosuke Fujii, Masumi Saitoh, Hiromichi Kuriyama, Takuya Konno
  • Publication number: 20170062527
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Application
    Filed: March 22, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takuya KONNO
  • Patent number: 9557828
    Abstract: An input information processing system, which is configured so as to enable an operator to efficiently conduct work without interruption, and processes input information that has been inputted using an input device, is configured so as to comprise: a display means for displaying data to be processed on a display screen; a first input device for inputting first input information; a second input device for inputting second input information; an acquisition means for acquiring a predetermined position in the data to be processed, which is displayed on the display screen of the display means, on the basis of the first input information inputted using the first input device; and control means for clearly showing the predetermined position in the data to be processed which was acquired by the acquisition means on the data to be processed displayed on the display screen of the display means, and for controlling the data to be processed which is displayed on the display screen of the display means on the basis of the
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: January 31, 2017
    Assignee: ZUKEN INC.
    Inventors: Takuya Konno, Yoshikuni Shibata