Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

Abstract: An input information processing system, which is configured so as to enable an operator to efficiently conduct work without interruption, and processes input information that has been inputted using an input device, is configured so as to comprise: a display means for displaying data to be processed on a display screen; a first input device for inputting first input information; a second input device for inputting second input information; an acquisition means for acquiring a predetermined position in the data to be processed, which is displayed on the display screen of the display means, on the basis of the first input information inputted using the first input device; and control means for clearly showing the predetermined position in the data to be processed which was acquired by the acquisition means on the data to be processed displayed on the display screen of the display means, and for controlling the data to be processed which is displayed on the display screen of the display means on the basis of the

Abstract: A heat-curable polymer paste comprising: (i) 100 parts by weight of a transparent polyester resin having a hydroxyl value of 1 to 10 mgKOH/g and a glass transition point (Tg) of 40 to 120° C., (ii) 1 to 30 parts by weight of a crosslinking agent comprising methoxymethyl imino melamine represented as formula (I); (C2N3)[—N(H)(CH2OCH3)]n[—N(CH2OCH3)2]3-n (I) wherein n is 1 to 3, and (iii) 50 to 200 parts by weight of an organic solvent.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a first interconnect portion provided on the substrate and including a plurality of interconnect layers separately stacked each other; a second interconnect portion provided separately from the first interconnect portion on the substrate and including the plurality of interconnect layers having a number of stacked layers same as a number of stacked layers of the first interconnect portion; a first pillar provided adjacent to the first interconnect portion and the second interconnect portion and extending in a stacking direction of the plurality of interconnect layers; and a plurality of conductive layers. The plurality of conductive layers is separately stacked each other, surrounding a side surface of the first pillar, and electrically connected to the first interconnect portion and the second interconnect portion.

Abstract: A heat-curable polymer paste comprising: (i) 100 parts by weight of a transparent polyester resin having a hydroxyl value of 1 to 10 mgKOH/g and a glass transition point (Tg) of 40 to 120° C., (ii) 1 to 30 parts by weight of a crosslinking agent comprising methoxymethyl imino melamine represented as formula (I); (C2N3)[—N(H)(CH2OCH3)]n[—N(CH2OCH3)2]3-n (I) wherein n is 1 to 3, and (iii) 50 to 200 parts by weight of an organic solvent.

Abstract: According to one embodiment, a device includes: word lines extending in a first direction, widths of the word lines in a second direction intersecting the first direction having a first width and a second width greater than the first width; bit lines provided above or under the word lines, the bit lines extending in the second direction, widths of the bit lines in the first direction having a third width and a forth width greater than the third width; storage elements; and a control circuit applying a potential for at least one of a plurality of non-selected word lines and a plurality of non-selected bit lines other than a selected word line and a selected bit line connected to a selected storage element, among the word lines and the bit lines, the potential applied thereto according to a width thereof.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.

Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.

Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.

Abstract: A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction, and a lower end of the second interconnection being located above the first interconnection; a plurality of third interconnections extending in a third direction, and the third interconnections being arranged in the second direction; a current limitation layer provided between the second interconnection and the third interconnections; a metal ion source layer provided between the current limitation layer and the third interconnections; a resistance change layer provided between the current limitation layer and the third interconnections; and a selector provided between the first interconnection and the lower end of the second interconnection.

Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a lower electrode layer, a variable resistance layer, and an upper electrode layer. The lower electrode layer is provided over a substrate. The variable resistance layer is provided on the lower electrode layer and is configured such that an electrical resistance of the variable resistance layer can be changed. The upper electrode layer is provided on the variable resistance layer. The variable resistance layer comprises a carbon nanostructure and metal atoms. The carbon nanostructure is stacked to have a plurality of gaps. The metal atoms are diffused into the gaps.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect, a second interconnect and a resistance change layer. The first interconnect extends in a first direction on a major surface of a substrate. The second interconnect extends in a second direction non-parallel to the first direction. The resistance change layer includes a conductive nanomaterial, the resistance change layer located between the first interconnect and the second interconnect and being capable of reversibly changing between a first resistance state and a second resistance state by a voltage applied or a current supplied through the first interconnect and the second interconnect. The resistance change layer has a density varied along a third direction generally perpendicular to the first direction and the second direction.

Abstract: The present invention pertains to an electroconductive paste for a solar cell electrode, which includes a first silver powder with a crystallite size of 58 nm, a second silver powder with a different crystallite size from that of the first silver powder, glass frit, and resin binder. The present invention also provides a solar cell having an electrode containing the aforementioned electroconductive paste.

Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.

Abstract: A nonvolatile memory device includes: a substrate; a first electrode formed on the substrate; a resistance change layer formed on the first electrode, the resistance change layer containing conductive nano-material; a second electrode formed on the resistance change layer; and an insulating buffer layer disposed between the first electrode and the resistance change layer, the insulating buffer layer containing conductive material dispersed therein for assuring the electric conductivity between the first electrode and the resistance change layer.

Abstract: A method of manufacturing a solar cell comprising steps of: (a) preparing a semiconductor substrate; (b) forming a metal thin film by vapor deposition on the back side of the semiconductor substrate; (c) applying a thick film conductive paste on the front side of the semiconductor substrate; and (d) firing the metal thin film and the applied thick film conductive paste to form a thin film electrode and a thick film electrode respectively.

Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.