Patents by Inventor Takuya Konno

Takuya Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9540536
    Abstract: A heat-curable polymer paste comprising: (i) 100 parts by weight of a transparent polyester resin having a hydroxyl value of 1 to 10 mgKOH/g and a glass transition point (Tg) of 40 to 120° C., (ii) 1 to 30 parts by weight of a crosslinking agent comprising methoxymethyl imino melamine represented as formula (I); (C2N3)[—N(H)(CH2OCH3)]n[—N(CH2OCH3)2]3-n (I) wherein n is 1 to 3, and (iii) 50 to 200 parts by weight of an organic solvent.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: January 10, 2017
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Takuya Konno, Naoto Nakajima
  • Publication number: 20160276276
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a first interconnect portion provided on the substrate and including a plurality of interconnect layers separately stacked each other; a second interconnect portion provided separately from the first interconnect portion on the substrate and including the plurality of interconnect layers having a number of stacked layers same as a number of stacked layers of the first interconnect portion; a first pillar provided adjacent to the first interconnect portion and the second interconnect portion and extending in a stacking direction of the plurality of interconnect layers; and a plurality of conductive layers. The plurality of conductive layers is separately stacked each other, surrounding a side surface of the first pillar, and electrically connected to the first interconnect portion and the second interconnect portion.
    Type: Application
    Filed: July 10, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke ARAYASHIKI, Kikuko SUGIMAE, Takuya Konno, Masayuki Ichige
  • Publication number: 20160060479
    Abstract: A heat-curable polymer paste comprising: (i) 100 parts by weight of a transparent polyester resin having a hydroxyl value of 1 to 10 mgKOH/g and a glass transition point (Tg) of 40 to 120° C., (ii) 1 to 30 parts by weight of a crosslinking agent comprising methoxymethyl imino melamine represented as formula (I); (C2N3)[—N(H)(CH2OCH3)]n[—N(CH2OCH3)2]3-n (I) wherein n is 1 to 3, and (iii) 50 to 200 parts by weight of an organic solvent.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 3, 2016
    Inventors: TAKUYA KONNO, NAOTO NAKAJIMA
  • Publication number: 20160035420
    Abstract: According to one embodiment, a device includes: word lines extending in a first direction, widths of the word lines in a second direction intersecting the first direction having a first width and a second width greater than the first width; bit lines provided above or under the word lines, the bit lines extending in the second direction, widths of the bit lines in the first direction having a third width and a forth width greater than the third width; storage elements; and a control circuit applying a potential for at least one of a plurality of non-selected word lines and a plurality of non-selected bit lines other than a selected word line and a selected bit line connected to a selected storage element, among the word lines and the bit lines, the potential applied thereto according to a width thereof.
    Type: Application
    Filed: March 9, 2015
    Publication date: February 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuya KONNO, Kikuko Sugimae, Masayuki Ichige
  • Patent number: 9224885
    Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 29, 2015
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Hideki Akimoto, Takuya Konno, Giovanna Laudisio, Patricia J. Ollivier, Michael Rose, Jerome David Smith, Richard John Sheffield Young
  • Patent number: 9203023
    Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 1, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masumi Saitoh, Chika Tanaka, Kikuko Sugimae, Takuya Konno
  • Publication number: 20150243887
    Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.
    Type: Application
    Filed: December 22, 2014
    Publication date: August 27, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masumi SAITOH, Chika TANAKA, Kikuko SUGIMAE, Takuya KONNO
  • Patent number: 9076723
    Abstract: A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction, and a lower end of the second interconnection being located above the first interconnection; a plurality of third interconnections extending in a third direction, and the third interconnections being arranged in the second direction; a current limitation layer provided between the second interconnection and the third interconnections; a metal ion source layer provided between the current limitation layer and the third interconnections; a resistance change layer provided between the current limitation layer and the third interconnections; and a selector provided between the first interconnection and the lower end of the second interconnection.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Matsunami, Masayuki Ichige, Takuya Konno, Kikuko Sugimae
  • Patent number: 8860000
    Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a lower electrode layer, a variable resistance layer, and an upper electrode layer. The lower electrode layer is provided over a substrate. The variable resistance layer is provided on the lower electrode layer and is configured such that an electrical resistance of the variable resistance layer can be changed. The upper electrode layer is provided on the variable resistance layer. The variable resistance layer comprises a carbon nanostructure and metal atoms. The carbon nanostructure is stacked to have a plurality of gaps. The metal atoms are diffused into the gaps.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Takuya Konno
  • Patent number: 8729517
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect, a second interconnect and a resistance change layer. The first interconnect extends in a first direction on a major surface of a substrate. The second interconnect extends in a second direction non-parallel to the first direction. The resistance change layer includes a conductive nanomaterial, the resistance change layer located between the first interconnect and the second interconnect and being capable of reversibly changing between a first resistance state and a second resistance state by a voltage applied or a current supplied through the first interconnect and the second interconnect. The resistance change layer has a density varied along a third direction generally perpendicular to the first direction and the second direction.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Konno, Kazuhiko Yamamoto
  • Patent number: 8723157
    Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Yasuyuki Baba, Takuya Konno
  • Patent number: 8721931
    Abstract: The present invention pertains to an electroconductive paste for a solar cell electrode, which includes a first silver powder with a crystallite size of 58 nm, a second silver powder with a different crystallite size from that of the first silver powder, glass frit, and resin binder. The present invention also provides a solar cell having an electrode containing the aforementioned electroconductive paste.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 13, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventor: Takuya Konno
  • Patent number: 8648323
    Abstract: A nonvolatile memory device includes: a substrate; a first electrode formed on the substrate; a resistance change layer formed on the first electrode, the resistance change layer containing conductive nano-material; a second electrode formed on the resistance change layer; and an insulating buffer layer disposed between the first electrode and the resistance change layer, the insulating buffer layer containing conductive material dispersed therein for assuring the electric conductivity between the first electrode and the resistance change layer.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Takuya Konno, Takeshi Yamaguchi
  • Publication number: 20140020743
    Abstract: A method of manufacturing a solar cell comprising steps of: (a) preparing a semiconductor substrate; (b) forming a metal thin film by vapor deposition on the back side of the semiconductor substrate; (c) applying a thick film conductive paste on the front side of the semiconductor substrate; and (d) firing the metal thin film and the applied thick film conductive paste to form a thin film electrode and a thick film electrode respectively.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Applicant: E I DU PONT DE NEMOURS AND COMPANY
    Inventor: TAKUYA KONNO
  • Publication number: 20140016398
    Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.
    Type: Application
    Filed: September 18, 2013
    Publication date: January 16, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Yasuyuki Baba, Takuya Konno
  • Publication number: 20130340821
    Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.
    Type: Application
    Filed: March 13, 2013
    Publication date: December 26, 2013
    Applicant: EI DU PONT DE NEMOURS AND COMPANY
    Inventors: Hideki AKIMOTO, Takuya KONNO, Giovanna LAUDISIO, Patricia J. OLLIVIER, Michael ROSE, Jerome David SMITH, Richard John Sheffield YOUNG
  • Patent number: 8569731
    Abstract: A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Konno, Hiroyuki Fukumizu, Kazuhito Nishitani
  • Publication number: 20130187856
    Abstract: An input information processing system, which is configured so as to enable an operator to efficiently conduct work without interruption, and processes input information that has been inputted using an input device, is configured so as to comprise: a display means for displaying data to be processed on a display screen; a first input device for inputting first input information; a second input device for inputting second input information; an acquisition means for acquiring a predetermined position in the data to be processed, which is displayed on the display screen of the display means, on the basis of the first input information inputted using the first input device; and control means for clearly showing the predetermined position in the data to be processed which was acquired by the acquisition means on the data to be processed displayed on the display screen of the display means, and for controlling the data to be processed which is displayed on the display screen of the display means on the basis of the
    Type: Application
    Filed: July 26, 2011
    Publication date: July 25, 2013
    Applicant: ZUKEN INC.
    Inventors: Takuya Konno, Yoshikuni Shibata
  • Patent number: 8482089
    Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 9, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Hideki Akimoto, Takuya Konno, Giovanna Laudisio, Patricia J. Ollivier, Michael Rose, Jerome David Smith, Richard John Sheffield Young
  • Patent number: 8465794
    Abstract: An objective of this present invention is to provide a conductive paste that could obtain good electrical property, for example series resistance in an electrode. An aspect of the present invention relates to a conductive paste which comprises electrically conductive powder; glass frit which comprises, based on weight percent (wt %) of the glass frit, 8-26 wt % of SiO2, 0.1-5 wt % of Al2O3, and 73-90 wt % of lead compound, wherein lead fluoride is contained in the range of 5-28 wt % based on the total weight of the lead compound; and organic medium.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: June 18, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Takuya Konno, Hisashi Matsuno, Brian J. Laughlin