Patents by Inventor Takuya Matsuo

Takuya Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220365182
    Abstract: A ranging device includes: a pulse generator; a controller that controls the pulse generator according to n (n is an integer greater than or equal to 4) types of packet generation codes indicating whether or not to expose or emit light in each of unit segments corresponding to distance segments into which a ranging range is divided; a light source; a solid-state image capturer; and a distance calculator that calculates the distance based on n types of signal values per unit segment obtained from the solid-state image capturer.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 17, 2022
    Inventors: Nobutaka NAKAMAE, Yuki MINAMI, Wataru MATSUMOTO, Mitsuhiko OTANI, Junichi MATSUO, Takuya ASANO, Haruka TAKANO, Shigeru SAITOU, Shinzo KOYAMA, Toshiya FUJII
  • Publication number: 20220363088
    Abstract: An envelope processing apparatus for enclosing an enclosure into an envelope conveyed to an enclosing position includes a conveyance roller that conveys the envelope to the enclosing position. A first envelope length calculator calculates a first envelope length of the envelope in an envelope conveyance direction in which the envelope is conveyed in a close state in which a flap of the envelope closes. A flap opener opens the flap while the conveyance roller conveys the envelope. A second envelope length calculator calculates a second envelope length of the envelope in the envelope conveyance direction in an open state in which the flap opens. A controller calculates a flap length of the flap in the envelope conveyance direction based on the first envelope length and the second envelope length. The controller controls enclosing of the enclosure into the envelope based on the flap length.
    Type: Application
    Filed: April 15, 2022
    Publication date: November 17, 2022
    Applicant: Ricoh Company, Ltd.
    Inventors: Shingo YOSHIZAWA, Michitaka SUZUKI, Nobuyoshi SUZUKI, Yuusuke SHIBASAKI, Shinji ASAMI, Takahiro MATSUDA, Kazuyoshi MATSUO, Makoto HIDAKA, Akira KUNIEDA, Takahiro WATANABE, Takuya MORINAGA
  • Patent number: 11485602
    Abstract: An embodiment of this disclosure provides a folding apparatus configured to stack and fold a designated number of sheets at a time. The folding apparatus includes a conveyor configured to sequentially convey the designated number of sheets, a stacker configured to temporarily store a sheet conveyed by the conveyor to stack the designated number of sheets, a sheet folding device configured to fold the designated number of sheets at a time, and control circuitry. The control circuitry is configured to cause the sheet folding device to fold the stored sheet in response to an occurrence of a sheet jam upstream from the stacker in a direction of sheet conveyance, in processing the designated number of sheets.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 1, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventors: Makoto Hidaka, Takahiro Watanabe, Tomohiro Furuhashi, Michitaka Suzuki, Fumiharu Yoneyama, Kazuyoshi Matsuo, Koki Sakano, Akira Kunieda, Takuya Morinaga, Yohsuke Haraguchi, Wataru Takahashi
  • Publication number: 20220338716
    Abstract: A treatment device and an endoscopic treatment method are disclosed. The treatment device includes a first pipeline that is made of material having electrical insulation, and includes an internal space; an electrode that is energizable with high frequency current; a distal-end tip that is attached to a distal end of the first pipeline, and includes a distal-end opening in communication with the internal space of the first pipeline; and a second pipeline that is inserted through the first pipeline and through which liquid can pass. The endoscopic treatment method includes puncturing a treatment target and performing a local injection using the treatment device.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 27, 2022
    Applicant: OLYMPUS CORPORATION
    Inventors: Nobuko MATSUO, Keiichi SATO, Takuya OKUMURA, Yuta HAYASHI
  • Patent number: 11476314
    Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masatomo Honjo, Hiroshi Matsukizono, Takuya Matsuo
  • Publication number: 20220288970
    Abstract: A rim portion of a vehicle wheel has an outer flange portion. In a region of the outer flange portion, a space portion between spoke portions is disposed on a radial-direction inner side, a first inclined surface and a second inclined surface are provided. The first inclined surface is provided on an axial-direction outer side of an outer flange outer circumferential portion. The second inclined surface is on an axial-direction outer side of an outer flange inner circumferential portion. The first inclined surface is formed to incline from the axial-direction outer side toward an axial-direction inner side as the first inclined surface extends from a radial-direction outer side end toward the radial-direction inner side. The second inclined surface is a surface formed to incline from the axial-direction inner side toward the axial-direction outer side as the second inclined surface extends from the radial-direction outer side toward the radial-direction inner side.
    Type: Application
    Filed: February 3, 2022
    Publication date: September 15, 2022
    Applicant: Mazda Motor Corporation
    Inventors: Masafumi ABURAME, Satoshi OKAMOTO, Akihiro NAKATA, Haruka TANIGUCHI, Shinji MATSUO, Hiroshi KUNINARI, Takuya MATSUDA
  • Patent number: 11411575
    Abstract: According to an embodiment, an information processing apparatus includes a computing unit and a compressing unit. The computing unit is configured to execute computation of an input layer, a hidden layer, and an output layer of a neural network. The compressing unit is configured to irreversibly compress output data of at least a part of the input layer, the hidden layer, and the output layer and output the compressed data.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: August 9, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Matsuo, Wataru Asano
  • Publication number: 20210275499
    Abstract: The invention relates to heterocyclic sulfonamide derivatives and their use in the treatment and prophylaxis of autoimmune, inflammatory, cardiovascular, neuronal, auditory, renal and metabolic mediated diseases, and to compositions containing said derivatives and processes for their preparation.
    Type: Application
    Filed: July 5, 2019
    Publication date: September 9, 2021
    Applicant: METRION BIOSCIENCES LIMITED
    Inventors: Marc ROGERS, Robert KIRBY, Gakujun SHOMI, Takuya MATSUO, Satoru KOBAYASHI, Junichiro KANAZAWA, Nobutaka YAMAOKA, Makoto TORIZUKA, Koichi SUZAWA
  • Patent number: 11018361
    Abstract: To provide a fuel cell stack device that is applicable to miniaturization of the device and does not require a pipe for discharging off-gas up to a combustion section. A fuel cell stack device including: a first manifold 2a for supplying fuel gas supplied from a reformer 12 to a plurality of fuel cells provided in a first cell stack from above, the first manifold being connected to upper ends of the plurality of fuel cells provided in the first cell stack 10a; and a second manifold 2b for recovering fuel gas discharged from the first cell stack, and supplying the recovered fuel gas to the plurality of fuel cells provided in the second cell stack from below, the second manifold being connected to lower ends of the plurality of fuel cells provided in the second cell stack 10b.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 25, 2021
    Assignee: MORIMURA SOFC TECHNOLOGY CO., LTD.
    Inventors: Naoki Watanabe, Toshiharu Otsuka, Akira Kawakami, Fumio Tsuboi, Takuya Matsuo, Takuya Hoshiko, Shuhei Tanaka
  • Patent number: 10981877
    Abstract: A production method of a compound represented by the formula [I]: or a pharmaceutically acceptable salt thereof, or a hydrate thereof.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 20, 2021
    Assignee: JAPAN TOBACCO INC.
    Inventors: Takahisa Motomura, Masafumi Inoue, Hirotsugu Ito, Takuya Matsuo, Koichi Suzawa, Hiroshi Yamamoto, Tsubasa Takeichi, Yasuyuki Kajimoto, Takashi Inaba, Takao Ito, Takahiro Yamasaki, Yukishige Ikemoto
  • Publication number: 20210013282
    Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: January 14, 2021
    Inventors: MASATOMO HONJO, HIROSHI MATSUKIZONO, TAKUYA MATSUO
  • Patent number: 10686468
    Abstract: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Matsuo, Atsushi Matsumura
  • Publication number: 20190375717
    Abstract: A production method of a compound represented by the formula [I]: or a pharmaceutically acceptable salt thereof, or a hydrate thereof.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 12, 2019
    Inventors: Takahisa Motomura, Masafumi Inoue, Hirotsugu Ito, Takuya Matsuo, Koichi Suzawa, Hiroshi Yamamoto, Tsubasa Takeichi, Yasuyuki Kajimoto, Takashi Inaba, Takao Ito, Takahiro Yamasaki, Yukishige Ikemoto
  • Patent number: 10505212
    Abstract: A solid oxide fuel cell apparatus 1 has: multiple fuel cell units 16; a module case 8 housing multiple fuel cell units; a heat insulating material 7 disposed to cover the area around the module case 8; a reformer 20 for reforming raw fuel gas using steam, thereby producing fuel gas; a combustion chamber 18 for combusting residual fuel gas and heating the reformer 20; a heat exchanger 23 for exchanging heat between oxidant gas and exhaust gas; and a steam generator 25, disposed within the heat insulating material 7 and on the outside of the module case 8, for exchanging heat between exhaust gas and water immediately after heat is exchanged in the heat exchanger 23, thereby producing steam.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 10, 2019
    Assignee: TOTO LTD.
    Inventors: Yousuke Akagi, Fumio Tsuboi, Takeshi Saito, Takuya Matsuo
  • Patent number: 10360101
    Abstract: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Kodama, Takayuki Itoh, Atsushi Matsumura, Takuya Matsuo
  • Patent number: 10355297
    Abstract: A solid oxide fuel cell apparatus 1 has: multiple fuel cell units 16; a module case 8 housing multiple fuel cell units; a heat insulating material 7 disposed to cover the area around the module case 8; a reformer 20 for reforming raw fuel gas using steam, thereby producing fuel gas; a combustion chamber 18 for combusting residual fuel gas and heating the reformer 20; a heat exchanger 23 for exchanging heat between oxidant gas and exhaust gas; and a steam generator 25, disposed within the heat insulating material 7 and on the outside of the module case 8, for exchanging heat between exhaust gas and water immediately after heat is exchanged in the heat exchanger 23, thereby producing steam.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 16, 2019
    Assignee: TOTO LTD.
    Inventors: Yousuke Akagi, Fumio Tsuboi, Takeshi Saito, Takuya Matsuo
  • Publication number: 20190181881
    Abstract: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.
    Type: Application
    Filed: August 28, 2018
    Publication date: June 13, 2019
    Inventors: Takuya MATSUO, Atsushi MATSUMURA
  • Patent number: 10306247
    Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 28, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya Matsuo, Takayuki Itoh, Takashi Watanabe, Atsushi Matsumura, Tomoya Kodama
  • Publication number: 20190124343
    Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya MATSUO, Takayuki Itoh, Takashi Watanabe, Atsushi Matsumura, Tomoya Kodama
  • Patent number: 10269831
    Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 23, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Seiji Kaneko, Yohsuke Kanzaki, Yutaka Takamaru, Keisuke Ide, Takuya Matsuo, Shigeyasu Mori, Hiroshi Matsukizono