Patents by Inventor Takuya Matsuo

Takuya Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100022523
    Abstract: The present invention relates to a novel 3-aminobenzamide compound represented by the following formula which effectively inhibits vanilloid receptor subtype 1 (VR1) activity (wherein, for example, R1 is a C1-6 alkyl group which may be substituted, R2 is a hydrogen atom, a C1-6 alkyl group or a C1-6 alkoxy group which may be substituted, R3 is a hydrogen atom or a C1-6 alkyl group, R4 is a C1-6 alkyl group, a C1-6 alkoxy group, or a halo C1-6 alkyl group, m is an integer of 1 to 5 and P is a carbon or hetero ring) or a pharmaceutically acceptable salt thereof. The pharmaceutical composition comprising as active ingredients the 3-aminobenzamide compound or a pharmaceutically acceptable salt thereof is useful for treating diseases involved in VR1 activity such as pain, acute pain, chronic pain, neuropathic pain, rheumatoid arthritis pain, and neuralgia.
    Type: Application
    Filed: April 27, 2009
    Publication date: January 28, 2010
    Applicant: Japan Tobacco Inc.
    Inventors: YOSHIHISA KOGA, SHINJI YATA, TAKASHI WATANABE, TAKUYA MATSUO, MASAHIRO SAKATA, WATARU KONDO
  • Patent number: 7625786
    Abstract: Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 1, 2009
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Misako Nakazawa, Hideto Ohnuma, Takuya Matsuo
  • Patent number: 7625785
    Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 1, 2009
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hideto Ohnuma, Masayuki Sakakura, Yasuhiro Mitani, Takuya Matsuo, Hidehito Kitakado
  • Patent number: 7528410
    Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 5, 2009
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Tatsuya Arao, Takeshi Noda, Takuya Matsuo, Hidehito Kitakado, Masanori Kyoho
  • Publication number: 20080003729
    Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
    Type: Application
    Filed: August 30, 2007
    Publication date: January 3, 2008
    Inventors: Hideto Ohnuma, Masayuki Sakakura, Yasuhiro Mitani, Takuya Matsuo, Hidehito Kitakado
  • Patent number: 7276402
    Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof. A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: October 2, 2007
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hideto Ohnuma, Masayuki Sakakura, Yasuhiro Mitani, Takuya Matsuo, Hidehito Kitakado
  • Publication number: 20070170513
    Abstract: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof.
    Type: Application
    Filed: March 30, 2007
    Publication date: July 26, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Saishi Fujikawa, Etsuko Asano, Tatsuya Arao, Takashi Yokoshima, Takuya Matsuo, Hidehito Kitakado
  • Patent number: 7217952
    Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: May 15, 2007
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Setsuo Nakajima, Aiko Shiga, Naoki Makita, Takuya Matsuo
  • Patent number: 7202149
    Abstract: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: April 10, 2007
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha Co., Ltd.
    Inventors: Saishi Fujikawa, Etsuko Asano, Tatsuya Arao, Takashi Yokoshima, Takuya Matsuo, Hidehito Kitakado
  • Publication number: 20070045730
    Abstract: A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.
    Type: Application
    Filed: October 4, 2006
    Publication date: March 1, 2007
    Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Takeshi Noda, Hidehito Kitakado, Takuya Matsuo
  • Publication number: 20070034874
    Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.
    Type: Application
    Filed: October 23, 2006
    Publication date: February 15, 2007
    Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Tatsuya Arao, Takeshi Noda, Takuya Matsuo, Hidehito Kitakado, Masanori Kyoho
  • Patent number: 7157321
    Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: January 2, 2007
    Assignees: Sharp Kabushiki Kaisha, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Takeshi Noda, Takuya Matsuo, Hidehito Kitakado, Masanori Kyoho
  • Patent number: 7145210
    Abstract: A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: December 5, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Takeshi Noda, Hidehito Kitakado, Takuya Matsuo
  • Patent number: 7141823
    Abstract: In a TFT with a GOLD structure, there is provided a structure which is able to improve an operating characteristic and reliability and reduce an off current value in order to reduce power consumption of a semiconductor device. The surface of LDD region (4) overlapped with a portion (7a) of a gate electrode through a gate insulating film (6) interposed therebetween is extremely flattened. Thus, it is possible to obtain a TFT structure which is capable of reducing a parasitic capacitance in the LDD region of the TFT with the GOLD structure, reducing an off current value, improving reliability, and enabling high speed operation.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: November 28, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hamada, Hidekazu Miyairi, Takuya Matsuo, Naoki Makita, Katsumi Nomura
  • Patent number: 7087504
    Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: August 8, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Setsuo Nakajima, Aiko Shiga, Naoki Makita, Takuya Matsuo
  • Patent number: 7015079
    Abstract: By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: March 21, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hidekazu Miyairi, Aiko Shiga, Katsumi Nomura, Naoki Makita, Takuya Matsuo
  • Publication number: 20060035939
    Abstract: The present invention relates to a novel 3-aminobenzamide compound represented by the following formula which effectively inhibits vanilloid receptor subtype 1 (VR1) activity (wherein, for example, R1 is a C1-6 alkyl group which may be substituted, R2 is a hydrogen atom, a C1-6 alkyl group or a C1-6 alkoxy group which may be substituted, R3 is a hydrogen atom or a C1-6 alkyl group, R4 is a C1-6 alkyl group, a C1-6 alkoxy group, or a halo C1-6 alkyl group, m is an integer of 1 to 5 and P is a carbon or hetero ring) or a pharmaceutically acceptable salt thereof. The pharmaceutical composition comprising as active ingredients the 3-aminobenzamide compound or a pharmaceutically acceptable salt thereof is useful for treating diseases involved in VR1 activity such as pain, acute pain, chronic pain, neuropathic pain, rheumatoid arthritis pain, and neuralgia.
    Type: Application
    Filed: July 14, 2005
    Publication date: February 16, 2006
    Applicant: Japan Tobacco Inc.
    Inventors: Yoshihisa Koga, Shinji Yata, Takashi Watanabe, Takuya Matsuo, Masahiro Sakata, Wataru Kondo
  • Publication number: 20060035882
    Abstract: To provide a compound having an excellent inhibitory effect on vanilloid receptor subtype 1 (VR1) activity which is effective in treating diseases to which the vanilloid receptor subtype 1 (VR1) activity is involved, such as pain, acute pain, chronic pain, neuropathic pain, rheumatoid arthritis pain, neuralgia, etc. and a pharmaceutical composition containing the compound.
    Type: Application
    Filed: July 15, 2005
    Publication date: February 16, 2006
    Applicant: Japan Tobacco Inc.
    Inventors: Yoshihisa Koga, Shinji Yata, Takashi Watanabe, Takuya Matsuo, Takayuki Yamasaki, Masahiro Sakata, Wataru Kondo, Hidekazu Ozeki, Yoshikazu Hori
  • Patent number: 6998641
    Abstract: In order to solve the problem of inferior gettering efficiency in the n-channel TFT, the present invention provides at an end of the source/drain regions of the n-channel TFT a highly efficient gettering region that contains both of an n-type impurity and a p-type impurity with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: February 14, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Misako Nakazawa, Hideto Ohnuma, Takuya Matsuo
  • Publication number: 20060009015
    Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.
    Type: Application
    Filed: September 9, 2005
    Publication date: January 12, 2006
    Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Setsuo Nakajima, Aiko Shiga, Naoki Makita, Takuya Matsuo