Abstract: This shooting system includes a plurality of cameras capable of capturing a subject that moves on a course from different directions, and a controller that receives a setting made by the user regarding a switch order of the plurality of cameras that temporally share continuous shooting of the subject that moves on the course, and switches output videos of the plurality of cameras in accordance with the set switch order.

Abstract: The invention has a purpose of improving applicability of a controller and a control method to a vehicle, the controller and the control method executing brake control in which primary information is selectively supplemented by secondary information that is information on an assumed state related to connection and disconnection of a clutch. The invention includes: a determination section 5A1 that determines whether an actual state and the assumed state, which are related to the connection and the disconnection of the clutch, match each other in accordance with a temporal change in the secondary information; and a brake control section 5A4 that executes the brake control by using the primary information but not the secondary information in the case where the determination section 5A1 determines that the actual state and the assumed state do not match each other.

Abstract: This shooting system includes a plurality of cameras capable of capturing a subject that moves on a course from different directions, and a controller that receives a setting made by the user regarding a switch order of the plurality of cameras that temporally share continuous shooting of the subject that moves on the course, and switches output videos of the plurality of cameras in accordance with the set switch order.

Abstract: A demultiplexing circuit provided in a display device including an active matrix substrate includes demultiplexers respectively corresponding to sets of source bus line groups obtained by dividing source bus lines in the active matrix substrate into groups with two or more source bus lines making up one set, and input terminals respectively corresponding to the demultiplexers. Each demultiplexer includes two or more main switching elements respectively corresponding to two or more source bus lines of the corresponding set, and two or more sub-switching elements respectively connected in parallel with the two or more main switching elements, the input terminals are respectively connected to the two or more source bus lines via the two or more main switching elements, and each of the two or more sub-switching elements is controlled to be turned off at a time later than a time when the corresponding main switching element is turned off.

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn?1) scanned prior to the n-th scanning signal line.

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation. [Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

Abstract: In each unit circuit constituting a shift register, as thin film transistors configured to lower a gate output, a thin film transistor whose state is controlled by a first reset signal and a thin film transistor whose state is controlled by a second reset signal are provided. Then, during the period in which a thin film transistor functioning as a buffer transistor is maintained in an ON state, the first reset signal changes from a low level to a high level, and then the second reset signal changes from a low level to a high level at a timing at which a corresponding gate bus line is to be changed from a selected state to an unselected state.

Abstract: A unit circuit that constitutes a shift register includes a gate output lowering transistor (T01) whose source terminal is supplied with a second gate low voltage (Vgl2) and a gate output reset transistor (T03) Whose source terminal is supplied with a first gate low voltage (Vgl1), as constituent elements associated with the lowering of gate output. At the time of lowering the gate output, the gate output lowering transistor (T01) is made to be in an on state, and thereafter the gate output reset transistor (T03) is made to be in the on state. In this case, the gate terminal of the gate output reset transistor (T03) is supplied with a scanning signal or a signal having a waveform equivalent to that of the scanning signal outputted from the unit circuit in a subsequent stage.

Abstract: When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.

Abstract: Steel materials for continuously variable transmissions sheaves, and methods for manufacturing a continuously variable transmission sheaves, are provided. In the disclosed steel materials for continuously variable transmission sheaves, the steel materials satisfy the following expressions: 13.9?Fn1?15.5, and 1.20?Fn2?4.35 (in which Fn1=7×Cr?6×Si+4×Mn; and Fn2=Al×N×104).

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Abstract: A lubricating oil tank includes: a tank casing having an introduction part into which lubricating oil is introduced and a discharge part through which the lubricating oil is discharged; a plurality of receiving parts which are disposed between the introduction part and the discharge part in the tank casing and which is configured to receive the lubricating oil introduced from the introduction part: and a lubricating oil delivery part which is configured to deliver the lubricating oil from one of the plurality of receiving parts to another one of the plurality of receiving parts between the plurality of receiving parts.

Abstract: Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.

Abstract: A configuration in which a voltage (a gate on voltage) of only one system is used as a voltage for turning scanning lines to a selected state is employed (single power supply system configuration). A unit circuit that constitutes a shift register within a gate driver includes a thin film transistor whose source terminal is connected to an output control node. In such a configuration, when the external power supply is stopped, a voltage supplied to a gate terminal of the thin film transistor and a voltage supplied to a drain terminal of the thin film transistor are set to the gate on voltage.

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.

Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.