Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.

Abstract: The present application discloses a scanning signal line drive circuit capable of reducing power consumption and narrowing a picture-frame while ensuring high-speed scanning for image display. First and second gate drivers 410, 420 are arranged to face each other via a display unit 500. Based on a DC buffer method, odd-numbered gate lines are driven by the first gate driver 410 while even-numbered gate bus lines are driven by the second gate driver 420, and when each gate bus line GLi is to be brought into a non-selected state, charges are released from both ends thereof. For this purpose, for example, the end portion of the odd-numbered gate bus line on the first gate driver side is connected to a buffer made up of the activation and inactivation transistors M10, M13L, and the end portion of the odd-numbered gate bus line on the second gate driver side is connected to the inactivation auxiliary transistor M13R.

Abstract: An account identification apparatus sets browsing authority for each of accounts such that browsing permission/prohibition is different for each of Web pages. Furthermore, the account identification apparatus causes a user terminal having accessed a predetermined Web site to transmit a request to each of the Web pages so as to acquire information about browsing permission/prohibition for each of the Web pages with regard to the user terminal and uses the acquired information about browsing permission/prohibition to identify an account with which the user terminal has logged in.

Abstract: A shift register is implemented that can increase the reliability of long-term operation regarding the driving of gate bus lines over a conventional configuration. The shift register is allowed to operate by clock signals of eight or more phases with an on-duty of less than ½. A stabilization node control portion brings a stabilization node (NB) to an on level for a period less than 50 percent of a normal operation period, based on two or more clock signals among the clock signals of eight or more phases, the stabilization node (NB) being connected to a gate terminal of a thin film transistor that contributes to the drawing of a potential of an output control node (NA) to a VSS potential.

Abstract: The present disclosure relates to an information processing apparatus, an information processing method, and a program making it possible to achieve camerawork corresponding to changes in various conditions when controlling multiple robot cameras. Position information about a subject is acquired, timing information indicating a passage of time is acquired, and on a basis of the timing information and the position information about the subject, camerawork control information controlling the camerawork of an image capture apparatus that captures the subject is generated. The present disclosure is applicable to a switcher apparatus that controls multiple robot cameras.

Abstract: When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.

Abstract: An image forming apparatus includes an electrophotographic photoreceptor including a conductive substrate, an undercoat layer containing a binder resin and metal oxide particles, disposed on the conductive substrate, and a photosensitive layer disposed on the undercoat layer; a charging unit that charges a surface of the electrophotographic photoreceptor; an electrostatic latent image-forming unit forming an electrostatic latent image on the charged surface of the electrophotographic photoreceptor; a developing unit developing the electrostatic latent image on the surface of the electrophotographic photoreceptor by using a developer containing a toner to form a toner image; and a transfer unit that transfers the toner image onto a surface of a transfer-receiving member, but not including a charge erasing member that erases charges on the surface of the electrophotographic photoreceptor. The photosensitive layer formed is 3.

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn?1) scanned prior to the n-th scanning signal line.

Abstract: The invention has a purpose of improving applicability of a controller and a control method to a vehicle, the controller and the control method executing brake control in which primary information is selectively supplemented by secondary information that is information on an assumed state related to connection and disconnection of a clutch. A determination section 5A1 and a brake control section 5A4 are provided, the determination section 5A1 determining whether an actual state related to the connection and the disconnection of the clutch matches the assumed state in accordance with a relationship between the secondary information and travel state information indicative of a travel state of the vehicle, and the brake control section 5A4 executing the brake control by using the primary information but not the secondary information in the case where the determination section 5A1 determines that the actual state does not match the assumed state.

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation. [Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

Abstract: A heater-integrated filter includes: a casing in which are formed an intake port for taking in a portion of process gas from a compressor and a discharge port for discharging the process gas; a filter body which is provided inside the casing and through which the process gas from the intake port passes; and rod-like heaters which are disposed inside the casing and along which the process gas that has passed through the filter body is capable of flowing toward the discharge port along the extension direction.

Abstract: A TFT circuit (101) includes a first node (N1) to which a first low potential (Vc) is supplied, a depression-type first TFT (21) which is arranged between the first node (N1) and low-potential wiring (11) for supplying a second low potential (Va) higher than the first low potential (Vc), and in which a drain terminal is connected to the first node, and a depression-type second TFT (22) which is arranged between the first TFT (21) and the low potential wiring (11) and in which a source terminal is connected to a source terminal of the first TFT, in which the first low potential (Vc) is supplied to a gate terminal of the second TFT, a second node (N2) enterable a floating state is formed between the source terminal of the first TFT and the source terminal of the second TFT, and the second node (N2) is connected to a sub-circuit (SC1) which is settable a potential of the second node (N2) to be lower than the second low potential (Va) and higher than the first low potential (Vc).

Abstract: The present invention provides a monolithic gate driver that includes fewer elements than in conventional configurations. In one aspect, a plurality of stages included in a shift register are divided into a plurality of stage circuit groups, where each stage circuit group includes the stage circuits of P adjacent stages (two stages, for example). Each stage circuit group includes a stabilization node and a stabilization node controller that controls the voltage of the stabilization node. The stabilization node controller includes: thin-film transistors in which the gate terminals thereof are connected to output control nodes, the drain terminals thereof are connected to the stabilization node, and the source terminals thereof are connected to an input terminal for a DC supply voltage; and a thin-film transistor for changing the voltage of the stabilization node to a high level.

Abstract: A compressor module includes: a rotational driving machine having an output shaft which is rotationally driven around an axis; a compressor which is disposed so as to be adjacent to the rotational driving machine in an axial direction in which the axis extends; a base plate which supports the rotational driving machine and the compressor from below in a vertical direction; and a storage tank which is configured to store a lubricating oil used in the rotational driving machine and the compressor. The storage tank has a tubular tank main body that is provided on an outer side of the base plate in a width direction and extends in a direction including the axial direction.

Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.

Abstract: A precharge circuit configured to precharge source bus lines is provided in a display device employing an SSD method. In the case where an n-channel TFT is employed, the precharge circuit applies a precharge voltage to the source bus line connected to the pixel formation portions to be subjected to data writing of a positive polarity, before a video signal is applied to the source bus line. In each horizontal scanning period, an SSD circuit switches the source bus line of a connection. destination of a data output line so that the video signal is applied to the source bus line connected to the pixel formation portions to be subjected to the data writing of a negative polarity relatively prior to the source bus line connected to the pixel formation portions to be subjected to the data writing of the positive polarity.