Abstract: In a semiconductor device having a diffusion-layer structure wherein high-concentration impurities are diffused into a low-impurity-concentration diffusion layer, two or more arrays of high-concentration diffusion layers are formed in each of diffusion layers constituting a collector region, an emitter region and a base region. Contacts are connected to their respective diffusion layers. A breakdown occurs on the diffusion layers, and heat generated therefrom is transmitted to the contacts.

Abstract: A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit.

Abstract: A semiconductor memory device invention having a data latch circuit disclosed in the present invention, comprising a plurality of bit lines to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group having an ability to directly transfer the data latched in the latch circuit, to the read our circuit without transferred to the memory cell.

Abstract: The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.

Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Abstract: A first transistor is connected between the gates of select transistors connected to two ends of a memory cell and a select line control circuit. A first gate line is connected to the gate of the first transistor. A first voltage control circuit controls the voltage of the first gate line to turn on or off the first transistor. A second transistor is connected between the control gate of the memory cell and a word line control circuit. A second gate line separated from the first gate line is connected to the gate of the second transistor. A second voltage control circuit controls the voltage of the second gate line to turn on or off the second transistor.

Abstract: The threshold voltage distribution for write operation into memory cells of a multi-level nonvolatile semiconductor memory device is precisely controlled and the verify result of written data is simultaneously detected for each page. For example, at the "10" data write time, excess write of "00" data which is a conventional problem is inhibited by controlling a path for transferring a lower bit to a bit line according to an upper bit. Further, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the upper bit. At the write time of "01" data, the bit line path is controlled by use of the lower bit and the write operation of "00" data is inhibited. Also, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the lower bit.