Patents by Inventor Tamotsu Usami

Tamotsu Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180047630
    Abstract: A method for manufacturing a semiconductor substrate according to the present invention includes a hydrogen layer forming step of forming a hydrogen layer on a first substrate formed of single crystal of a first semiconductor material, a bonding step of bonding the first substrate and a temporary substrate, a first separation step of separating the first substrate with the hydrogen layer as a boundary and leaving a separated surface side of the first substrate as a first thin film layer on the temporary substrate, a support layer forming step of forming a support layer formed of a second semiconductor material on the temporary substrate on which the first thin film layer is left, a second separation step of removing the temporary substrate, and a cutting step of cutting a peripheral edge portion of the substrate.
    Type: Application
    Filed: March 1, 2016
    Publication date: February 15, 2018
    Applicant: MTEC CORPORATION
    Inventors: Mitsuharu KATO, Tamotsu USAMI, Tadashi SHIMADA
  • Patent number: 8217466
    Abstract: Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: July 10, 2012
    Assignee: Jjtech Co., Ltd.
    Inventors: Kanji Otsuka, Fumio Mizuno, Munekazu Takano, Tamotsu Usami
  • Publication number: 20110042120
    Abstract: A wire (a twisted pair cable) that transmits a gigahertz band signal and that is provided with a pair of core wires that are twisted with each other, a first insulation coating material, a second insulation coating material, and a shield material that shields evanescent waves emitted from the pair of core wires. The pair of core wires have a twisting pitch, a diameter, and a spacing so that the wire has a characteristic impedance of 100 to 200? and the phases of the TEM (Transverse Electro-Magnetic) wave and the evanescent wave that are emitted from the pair of core wires are matched.
    Type: Application
    Filed: February 2, 2009
    Publication date: February 24, 2011
    Applicants: IBIDEN CO., LTD., NEC CORPORATION, FUJITSU SEMICONDUCTOR LIMITED, FUJI XEROX CO., LTD., KYOCERA CORPORATION
    Inventors: Kanji Otsuka, Tamotsu Usami, Chihiro Ueda, Yutaka Akiyama
  • Patent number: 7872612
    Abstract: An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 18, 2011
    Assignees: Renesas Electronics Corporation, Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, Fuji Xerox Co., Ltd., Ibiden Co., Ltd, Kyocera Corporation
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Chihiro Ueda
  • Patent number: 7791852
    Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: September 7, 2010
    Assignees: Fujitsu Microelectronics Limited, OKI Semiconductor Co., Ltd., Kyocera Corporation, Kabushiki Kaisha Toshiba, Fuji Xerox Co., Ltd., Renesas Technology Corp
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Tsuneo Ito, Yuko Tanba
  • Patent number: 7631422
    Abstract: A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 15, 2009
    Assignees: Rohm Co., Ltd., Oki Semiconductor Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Renesas Technology Corp., Fujitsu Microelectronics Limited, Panasonic Corporation
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Publication number: 20090096029
    Abstract: Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.
    Type: Application
    Filed: August 1, 2006
    Publication date: April 16, 2009
    Inventors: Kanji Otsuka, Fumio Mizuno, Munekazu Takano, Tamotsu Usami
  • Publication number: 20080316136
    Abstract: An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 25, 2008
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Chihiro Ueda
  • Patent number: 7446567
    Abstract: Apparatus for transmitting a digital signal within, for example, an integrated circuit includes a signal transmission line with a directional coupler at one or both ends. The directional coupler blocks the direct-current component of the digital signal while transmitting the alternating-current component, including enough higher harmonics to transmit a well-defined pulse waveform. A suitable directional coupler consists of two adjacent line pairs in materials with different dielectric constants. The apparatus may also include a driver of the inverter type, a receiver of the differential amplifier type, a terminating resistor, and a power-ground transmission line pair for supplying power to the driver. An all-metallic transmission-line structure is preferably maintained from the output interconnections in the driver to the input interconnections in the receiver.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: November 4, 2008
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., Renesas Technology Corp., Rohm Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 7446625
    Abstract: An impedance conversion device has four conductors arranged so that the first and second conductors form a transmission line having a first characteristic impedance, the third and fourth conductors form a transmission line having the first characteristic impedance, the first and third conductors form a transmission line having a second characteristic impedance, and the second and fourth conductors form a third transmission line having the second characteristic impedance. The second and fourth conductors are interconnected at proximate ends through a resistance equal to the first characteristic impedance. The third and fourth conductors are interconnected at proximate ends through a resistance equal to the second characteristic impedance. The lateral dimensions of the impedance conversion device are small enough to permit insertion in a stacked pair line.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: November 4, 2008
    Assignees: Oki Electric Industry Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Limited, Renesas Technology Corp., Kyocera Corporation, Fuji Xerox Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama
  • Publication number: 20080042686
    Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 21, 2008
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Tsuneo Ito, Yuko Tanba
  • Patent number: 7295032
    Abstract: A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: November 13, 2007
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Kanji Otsuka, Tamotsu Usami, Tetsuya Higuchi, Eiichi Takahashi, Yuji Kasai, Masahiro Murakawa
  • Patent number: 7280385
    Abstract: A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: October 9, 2007
    Assignees: Kabushiki Kaisha Toshiba, Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, NEC Corporation, Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., Renesas Technology Corp., Rohm Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Publication number: 20070176708
    Abstract: An impedance conversion device has four conductors arranged so that the first and second conductors form a transmission line having a first characteristic impedance, the third and fourth conductors form a transmission line having the first characteristic impedance, the first and third conductors form a transmission line having a second characteristic impedance, and the second and fourth conductors form a third transmission line having the second characteristic impedance. The second and fourth conductors are interconnected at proximate ends through a resistance equal to the first characteristic impedance. The third and fourth conductors are interconnected at proximate ends through a resistance equal to the second characteristic impedance. The lateral dimensions of the impedance conversion device are small enough to permit insertion in a stacked pair line.
    Type: Application
    Filed: August 9, 2006
    Publication date: August 2, 2007
    Applicants: Oki Electric Industry Co., Ltd., KABUSHIKI KAISHA TOSHIBA, FUJITSU LIMITED, Renesas Technology Corp., KYOCERA Corporation, FUJI XEROX CO., LTD.
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama
  • Patent number: 7190188
    Abstract: To transmit a high-speed digital signal of several tens GHz via a differential line by connecting a differential line referring to the ground to differential lines not referring to the ground, there is provided a signal transmission system which transmits a digital signal between circuit blocks via a signal transmission line, each of the circuit blocks basically including a functional circuit, a reception/transmission circuit formed separately from the functional circuit and an impedance-matched transmission line (115) formed between reception and transmission ends of the reception/transmission circuit; a differential line (105) referring to the ground (110), led out from a differential output driver, being formed from differential signal lines disposed symmetrically with respect to the ground (110) in the circuit block, only differential pair lines (111, 112) not referring to the ground being extended directly from the differential signal lines disposed symmetrically with respect to the ground in the signal
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: March 13, 2007
    Assignees: Sony Corporation, Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd., Fujitsu Limited, Rohm Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 7173449
    Abstract: Signal transmission technology for transmitting 20–50 GHz band digital high speed signals, while keeping to the system structure and element structure of the prior art is provided. A signal transmission system is provided in which the driver and the receiver comprise the logic circuit and the memory circuit for a transistor extending an entire electronic circuit, and wherein the driver is connected to the receiver via a signal transmission line, and to the power source Vdd via the power source/ground transmission line, and the receiver circuits and the driver and receiver all have substantially differential input and differential output, and at the output terminal of the substantially differential output of the driver there are no connections to a power source or a ground and the receiver receives signals by detecting potential difference of a substantially differential input signal and there are no distribution wires in the signal transmission lines.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: February 6, 2007
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Publication number: 20060226927
    Abstract: A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.
    Type: Application
    Filed: May 25, 2006
    Publication date: October 12, 2006
    Applicants: ROHM CO., LTD., OKI ELECTRIC INDUSTRY CO., LTD., SANYO ELECTRIC CO., LTD., SONY CORPORATION, KABUSHIKI KAISHA TOSHIBA, NEC CORPORATION, Sharp Kabushiki Kaisha, FUJITSU LIMITED, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., RENESAS TECHNOLOGY CORPORATION
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 7116184
    Abstract: A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: October 3, 2006
    Assignees: Rohm Co., Ltd, Oki Electric Industry Co., Ltd, Sanyo Electric Co., Ltd, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Fujitsu Limited, Matsushita Electric Industrial, Renesas Technology Corp.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 7113002
    Abstract: A differential signal transmission cable structure for transmitting differential signals having GHz frequency band in the present invention is provided with a differential signal transmission pair cable 30 connecting a driver circuit 23a and a receiver circuit 23b, for transmitting differential signals having GHz frequency band, and a power supply ground transmission pair cable 31 connecting ground and a first power supply 26a connected to the driver circuit and ground and a second power supply 26b connected to the receiver circuit. Further characteristic impedance of the differential signal transmission pair cable is matched to that of the driver circuit and the receiver circuit, thereby enabling TEM waves of differential signals having GHz frequency band transmission mode to be maintained when the differential signals are transmitted.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 26, 2006
    Assignee: Fujikura Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami, Chihiro Ueda, Yutaka Akiyama, Osamu Koyasu
  • Publication number: 20060203586
    Abstract: A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 14, 2006
    Inventors: Kanji Otsuka, Tamotsu Usami