Patents by Inventor Tang Wu

Tang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894024
    Abstract: An information handling system storage bay accepts 2.5 inch and 3.5 inch storage drives held in a storage drive carrier sized to hold 3.5 inch storage drives and having an adapter that couples to the storage drive carrier to adapt it to hold 2.5 inch drives. The storage drive carrier is manufactured as a contiguous piece from a mold with hard plastic to integrate the adapter so that the adapter breaks free to couple to the storage drive carrier when a small size drive is to be held. Snaps in the contiguous piece couple with the adapter after the adapter is broken free to store the adapter when a larger sized drive is held by the storage drive carrier.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 6, 2024
    Assignee: Dell Products L.P.
    Inventors: Edward D. Geist, Jing-Tang Wu
  • Publication number: 20240012455
    Abstract: A variable holder module secures a variety of different expansion cards that may be installed within a computer or other information handling system. The holder module has a multi-sided component that is orientable according to which expansion card is to be secured within the computer. Each side of the component may thus correspond to a different one of the expansion cards. Once the expansion card is determined, a human or robotic picker need only orient component to the side that corresponds to the make/model of the expansion card. The holder module is thus adaptable to secure many different expansion cards that may be installed within the computer.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Jing-Tang Wu, Tung-Yi Chen, Andrew O. Ingalls
  • Patent number: 11864467
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Patent number: 11844283
    Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Tang Wu, Meng Yu Wu, Szu-Hua Wu, Chin-Szu Lee
  • Patent number: 11836008
    Abstract: A configurable component receptacle which includes a holder portion and a flexible portion, the flexible portion enabling the holder portion of the configurable component receptacle to be in a horizontal configuration and a pivoted configuration, the holder portion and the flexible portion being configured from a single piece of material. The configurable component receptacle is attached to a frame of an information handling system, the configurable component receptable enabling configuration of the information handling system with a plurality of component options.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Jing-Tang Wu, Tung-Yi Chen
  • Publication number: 20230389438
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Publication number: 20230380291
    Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Yu-Jen CHIEN, Jung-Tang Wu, Szu-Hua Wu, Chin-Szu Lee, Meng-Yu Wu
  • Publication number: 20230369044
    Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Jung-Tang Wu, Yu-Jen Chien, Szu-Hua Wu, Chin-Szu Lee, Yao-Shien Huang
  • Patent number: 11795021
    Abstract: A method for assembling an information handling system display may include attaching a first side of a strip of double-sided tape to a display panel cover. A display panel may then be aligned with the display panel cover, and, when aligned, the display panel may be in contact with a release paper attached to a second side of the double-sided tape. The release paper may then be removed from the double-sided tape while the display panel is in contact with the release paper. A first surface of the display panel may be attached to the second side of the double-sided tape as the release paper is removed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: October 24, 2023
    Assignee: Dell Products L.P.
    Inventors: Chin-Chung Wu, Tsai Chien Lin, James Gossett, Wan Li Chen, Jing-Tang Wu, Hung-Chun Huang
  • Patent number: 11791206
    Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Pao-Sheng Chen, Pei-Hsuan Lee, Szu-Hua Wu, Chih-Chien Chi
  • Publication number: 20230315158
    Abstract: A configurable component receptacle which includes a holder portion and a flexible portion, the flexible portion enabling the holder portion of the configurable component receptacle to be in a horizontal configuration and a pivoted configuration, the holder portion and the flexible portion being configured from a single piece of material. The configurable component receptacle is attached to a frame of an information handling system, the configurable component receptable enabling configuration of the information handling system with a plurality of component options.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Dell Products L.P.
    Inventors: Jing-Tang Wu, Tung-Yi Chen
  • Patent number: 11749524
    Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Yu-Jen Chien, Szu-Hua Wu, Chin-Szu Lee, Yao-Shien Huang
  • Patent number: 11720726
    Abstract: A global computer aided engineering (CAE) model representing an electronic product that contains solder joints and an individual detailed solder joint model are received. The solder joint model can include a solder ball, one or more metal pads, a portion of printed circuit board, and a portion of semiconductor chip component. The global CAE model includes locations of the solder joints to be evaluated in a drop test simulation. The solder joint model is replicated at each location to create a local CAE model via a geometric relationship between the global CAE model and the local CAE model. Simulated physical behaviors of the product under a design condition are obtained in a co-simulation using the global CAE model in a first time scale and the local CAE model in a second time scale. Simulated physical behaviors are periodically synchronized based on kinematic and force constraints.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: August 8, 2023
    Assignee: ANSYS Inc.
    Inventors: Cheng-Tang Wu, Wei Hu, Dandan Lyu, Siddharth Shah, Ashutosh Srivastava
  • Patent number: 11696510
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang Wu, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Publication number: 20230137291
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang WU, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Publication number: 20230130498
    Abstract: An information handling system storage bay accepts 2.5 inch and 3.5 inch storage drives held in a storage drive carrier sized to hold 3.5 inch storage drives and having an adapter that couples to the storage drive carrier to adapt it to hold 2.5 inch drives. The storage drive carrier is manufactured as a contiguous piece from a mold with hard plastic to integrate the adapter so that the adapter breaks free to couple to the storage drive carrier when a small size drive is to be held. Snaps in the contiguous piece couple with the adapter after the adapter is broken free to store the adapter when a larger sized drive is held by the storage drive carrier.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 27, 2023
    Applicant: Dell Products L.P.
    Inventors: Edward D. Geist, Jing-Tang Wu
  • Publication number: 20230073308
    Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Jung-Tang WU, Szu-Ping TUNG, Szu-Hua WU, Shing-Chyang PAN, Meng-Yu WU
  • Patent number: 11592912
    Abstract: Clickpad structures may be attached to surfaces of an information handling system using material stacks comprising an elastic material, such as a sponge, which can preload a force on the clickpad surface. The preloaded force reduces a gap between the clickpad switch and contact point, which reduces instability, rattling, and other negative experiences with the clickpad surface experienced by a user. According to an embodiment, an input device for an information handling system includes a clickpad surface having a first side configured to receive user input and a second side opposite the first side; a first coupling stack comprising a first elastic material with a first thickness; and a second coupling stack comprising a second elastic material with a second thickness, wherein each of the coupling stacks is attached to the clickpad surface and a surface of the information handling system by adhesives.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Jing-Tang Wu, Shih-Wei Yang, Chia-Chi Ho, Ya-Chen Tsai
  • Patent number: 11586253
    Abstract: An information handling system display removably couples to a housing with a sliding structure of the display that engages a coupling structure disposed at opposing sides of the housing. For example, the sliding structure is a member that aligns under a lip formed in the coupling structure. In one embodiment, the sliding structure comprises plural pins extending from opposing sides of the display to enter channels at the side of the housing that direct the pins under a lip at the base of the channel.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: February 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Chin-Chung Wu, Tsai Chien Lin, James D. Gossett, Jing-Tang Wu, Cheng-Pu Zhu
  • Patent number: 11515474
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu