Abstract: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.

Abstract: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Abstract: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Abstract: A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.

Abstract: A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.

Abstract: A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

Abstract: A system for managing a cluster of nodes, the cluster comprising a plurality of groups of nodes, each node being associated with a vote, the system further comprising an arbitration device, the arbitration device being associated with a number of votes dependent on the number of nodes in the cluster, each node further being associated with a cluster manager, one of the cluster managers for each group being operable: if the group is in communication with the arbitration device, to determine whether the group has the greatest number of votes, including the votes of the arbitration device; if the arbitration device is operative, but the group is not in communication with the arbitration device, to determine whether the group meets the quorum without adjusting the quorum; and if the arbitration device is not operative, to determine whether the group meets the quorum after adjusting the quorum.

Abstract: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments.

Abstract: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments.

Abstract: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Abstract: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Abstract: A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion.

Abstract: One SONOS-type device contains (a) a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric, and (b) a semiconductor channel region that contains polysilicon. Another SONOS-type device contains a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric. The device is located in a monolithic three dimensional memory array.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.

Abstract: In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.