Abstract: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.

Abstract: A method and apparatus is disclosed for selecting a cluster in a group of nodes in which a token is assigned to a first node of a group of nodes, subgroups of nodes that are interconnected are identified and if the two largest said subgroups comprise equal numbers of nodes then the subgroup containing the node to which said token is assigned is selected as the cluster.

Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

Abstract: A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

Abstract: A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element, wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.

Abstract: In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.