Patents by Inventor Tanmoy Roy
Tanmoy Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941357Abstract: Various embodiments of the present invention provide methods, apparatus, systems, computing devices, computing entities, and/or the like for performing text similarity determination. Certain embodiments of the present invention utilize systems, methods, and computer program products that perform text similarity determination by using at least one of Word Mover's Similarity measures, Relaxed Word Mover's Similarity measures, and Related Relaxed Word Mover's Similarity measures.Type: GrantFiled: June 23, 2021Date of Patent: March 26, 2024Assignee: OPTUM TECHNOLOGY, INC.Inventors: Suman Roy, Amit Kumar, Sourabh Kumar Bhattacharjee, Shashi Kumar, William Scott Paka, Tanmoy Chakraborty
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Patent number: 11889675Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.Type: GrantFiled: November 3, 2022Date of Patent: January 30, 2024Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tushar Sharma, Tanmoy Roy, Shishir Kumar
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Patent number: 11829730Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: GrantFiled: September 8, 2022Date of Patent: November 28, 2023Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
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Patent number: 11798615Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: GrantFiled: April 15, 2022Date of Patent: October 24, 2023Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy
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Patent number: 11776650Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: GrantFiled: June 22, 2022Date of Patent: October 3, 2023Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Anuj Grover
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Patent number: 11749343Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.Type: GrantFiled: January 18, 2022Date of Patent: September 5, 2023Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover
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Patent number: 11742045Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.Type: GrantFiled: April 5, 2021Date of Patent: August 29, 2023Assignee: STMicroelectronics International N.V.Inventors: Rohit Bhasin, Shishir Kumar, Tanmoy Roy, Deepak Kumar Bihani
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Publication number: 20230186983Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: STMicroelectronics International N.V.Inventors: Anuj GROVER, Tanmoy ROY, Nitin CHAWLA
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Publication number: 20230091970Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.Type: ApplicationFiled: November 3, 2022Publication date: March 23, 2023Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tushar SHARMA, Tanmoy ROY, Shishir KUMAR
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Patent number: 11605424Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.Type: GrantFiled: July 14, 2021Date of Patent: March 14, 2023Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy, Nitin Chawla
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Publication number: 20230004354Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nitin CHAWLA, Tanmoy ROY, Anuj GROVER, Giuseppe DESOLI
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Patent number: 11532633Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.Type: GrantFiled: September 30, 2021Date of Patent: December 20, 2022Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tushar Sharma, Tanmoy Roy, Shishir Kumar
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Patent number: 11474788Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: GrantFiled: June 2, 2020Date of Patent: October 18, 2022Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
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Publication number: 20220328118Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: ApplicationFiled: June 22, 2022Publication date: October 13, 2022Applicant: STMicroelectronics International N.V.Inventors: Tanmoy ROY, Anuj GROVER
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Publication number: 20220238150Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Applicant: STMicroelectronics International N.V.Inventors: Anuj GROVER, Tanmoy ROY
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Patent number: 11398289Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: GrantFiled: January 25, 2021Date of Patent: July 26, 2022Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Anuj Grover
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Patent number: 11393532Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.Type: GrantFiled: April 13, 2020Date of Patent: July 19, 2022Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Tanuj Kumar, Shishir Kumar
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Patent number: 11335397Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: GrantFiled: August 14, 2020Date of Patent: May 17, 2022Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy
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Publication number: 20220139453Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Applicant: STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Tanmoy ROY, Anuj GROVER
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Patent number: 11257543Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.Type: GrantFiled: June 5, 2020Date of Patent: February 22, 2022Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover