Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.