Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Abstract: A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.

Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract: A system and method for determining the desired decoupling components for a power distribution system having a voltage regulator module. The system may employ a mathematical model of a voltage regulator circuit, such as a switching voltage regulator. The mathematical model may be a SPICE model, or a circuit model in another format. The method may include simulating the operation of the power distribution system to obtain a estimate of the bulk capacitance required for effective decoupling. For digital systems, the method may include a cycle-by-cycle simulation of the power distribution system, wherein the simulation occurs over a number of clock cycles. The performance of the power distribution system may then be analyzed for each simulated clock cycle. The simulation may also include analyzing the transient responses and loop stability of the power distribution.

Abstract: A system and method for determining the desired decoupling capacitors for power distribution systems having frequency dependent target impedance. In one embodiment, the target impedance may be a function of frequency, and thus may vary in value over a frequency range from 0 Hz to a corner frequency. A specific quantity of decoupling capacitors may be selected to provide decoupling for the power distribution for a given frequency within the frequency range. A total impedance provided by the specific quantity of selected decoupling capacitors may be calculated and compared to the calculated target impedance for the given frequency. If the total impedance provided by the specific quantity of selected decoupling capacitors is greater than the target impedance for the given frequency, the impedance may be adjusted by changing the quantity of capacitors. Capacitors may continue to be added until the total impedance is less than the target impedance.

Abstract: A system and method for analyzing simultaneous switching noise. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated.

Abstract: A method for determining the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components.

Abstract: A system and method for determining the desired decoupling capacitors for power distribution systems having frequency dependent target impedance. In one embodiment, the target impedance may be a function of frequency, and thus may vary in value over a frequency range from 0 Hz to a corner frequency. A specific quantity of decoupling capacitors may be selected to provide decoupling for the power distribution for a given frequency within the frequency range. A total impedance provided by the specific quantity of selected decoupling capacitors may be calculated and compared to the calculated target impedance for the given frequency. If the total impedance provided by the specific quantity of selected decoupling capacitors is greater than the target impedance for the given frequency, the impedance may be adjusted by changing the quantity of capacitors. Capacitors may continue to be added until the total impedance is less than the target impedance.

Abstract: A method for determining the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components.

Abstract: A system and method for measuring the equivalent series resistance (ESR) of one or more capacitors using an impedance analyzer, whereby the capacitors are joined to the impedance analyzer with a conductive adhesive. The conductive adhesive may advantageously provide for an electrically and mechanically stable connection between the capacitor and the remainder of the electrical circuit used to measure the ESR of the capacitor. The conductive adhesive may include heat activated or cold solder, or conductive putty. The system comprises a measuring unit for sweeping a frequency range to find the minimum impedance for the capacitor and a connector assembly for holding the capacitor in an electrically and mechanically stable connection using the conductive adhesive. The connector assembly includes a mating portion adapted for electrically connecting the connector assembly to an I/O port of the measuring unit and a terminal portion that accommodates a connection to the capacitor using the conductive adhesive.