Abstract: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

Abstract: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

Abstract: This invention provides a request controlling apparatus, processor and method. The request controlling apparatus is connected to a request storage unit and includes: a queue unit storing flag recording region configured to record a storing flag corresponding to a queue unit in the request storage unit, a comparing means configured to judge whether a incoming first queue unit corresponds to a same message as an already existing queue unit, where the already existing queue unit is in the request storage unit and a flag setting means is configured to set the storing flag corresponding to the already existing queue unit in the queue unit storing flag recording region, to indicate that a message state related to the already existing queue unit will not be stored if the first queue unit corresponds to the same message as in the already existing queue unit.

Abstract: The invention discloses a method and system of maintaining states for the request queue of a hardware accelerator, wherein the request queue stores therein at least one Coprocessor Request Block (CRB) to be input into the hardware accelerator, the method comprising: receiving, in response to a CRB specified by the request queue is about to enter the hardware accelerator, the state pointer of the specified CRB; acquiring physical storage locations of other CRBs in the request queue that are stored in the request queue and are the same as the state pointer of the specified CRB; controlling the input of the specified CRB and the state information required for processing the specified CRB into a hardware buffer; receiving the state information of the specified CRB that has been processed in the hardware accelerator; if the above physical storage locations are not vacant, then making physical storage locations that are closest on the request queue of the specified CRB as the selected location and storing the recei

Abstract: A stereoscopic image display device is for use with shutter glasses having left and right shutter lenses and includes a display processor, a display screen, a signal generator, and a signal transmitter. The display processor is for receiving a video input signal and outputting a video output signal sequence according to a frame sync signal acquired from the video input signal. The display screen is for receiving the video output signal sequence corresponding to a sequence of left-eye and right-eye images and displays the left-eye and right-eye images in an alternating manner according to the frame sync signal. The signal generator is for generating a shutter sync control signal that is transmitted to the shutter glasses by the signal transmitter for controlling duty cycles of alternating operations of the shutter glasses according to the frame sync signal.

Abstract: An electrical circuit for use as a string of lights in one embodiment includes a rectifier for converting AC into DC; and a plurality of lamps connected in series, each lamp having an LED, and wherein at least one of the lamps each has a Zener diode connected in series with the LED, a positive terminal of the lamp proximate the rectifier is connected to a positive terminal of an output of the rectifier, and a negative terminal of the lamp distal the rectifier is connected to a negative terminal of the output of the rectifier. In another embodiment, the Zener diode is replaced with a resistor. Hence, no resistors are provided externally of the lamp.

Abstract: In one embodiment an electrical circuit for use as a string of lights includes a load comprising a plurality of lamps connected in series, the lamps comprising a first group of lamps including an LED and a first Zener diode in parallel therewith, and a second group of lamps including an incandescent light bulb and a second Zener diode in parallel therewith; and a rectifier for converting a source of AC into DC which is supplied to the load. The first group of lamps are alternate with the second group of lamps.

Abstract: A processing unit coupled to a bus for accelerating data transmission and a method for accelerating data transmission. The present invention provides a streaming data transmission mode in which a plurality of data blocks are transmitted via one handshake. The present invention employs handshake save policy, when a processing unit sends a request comprising a plurality of data blocks on a bus, a cache or memory will perform address matching to judge whether there is any hit data block. If there is any hit data block, the cache or memory only needs to reply once and then start to continuously transmit the hit data blocks it possesses. Thus, a separate handshake for each data block is no longer needed.

Abstract: An embodiment of the invention provides an extremum route determining engine and method. The engine includes a memory for storing a path with a weight in a graph and an extremum route determining logic circuit. The logic circuit includes a path reading section for reading the path in the graph, a writing section for updating the weight of the read path according to a predetermined extremum requirement and writing the path whose weight is updated into the memory, and an extremum route determining section for determining an extremum route. The method includes reading a stored path in a graph, the path having a weight, updating the weight of the read path and writing the path whose weight has been updated into a memory, and determining an extremum route. An embodiment of the invention improves the processing speed of extremum route determination.

Abstract: A method and apparatus for lock allocation control. When a processor core acquires a lock, other processor cores do not need to constantly poll memory to check whether the required lock is released. Instead, other processor cores will be in sleep state and the next processor core needed will be selectively woken up based on predetermined rule, such that an out-of-order lock contention procedure is turned into an in-order lock allocation procedure. By selectively waking up a processor core that is in sleep state, the method and apparatus can avoid occupying a large amount of bus bandwidth, can avoid cache misses, and can save power consumption of chip.

Abstract: A holder is for holding an electronic device, and includes a housing, a support frame, and a resilient element. The housing is disposed on a rear face of the electronic device, defines a receiving space, and includes a barrier plate abutting against one side of the electronic device. The support frame is disposed in the receiving space and is movable relative to the housing. The support frame includes a catch member which is exposed from the housing, which is disposed opposite to the barrier plate, and which is engaged with a retaining hole in the rear face, and a push button portion exposed from the housing. The push button portion is operable to permit disengagement of the catch member from the retaining hole. The resilient element is disposed in the receiving space to provide the catch member with a restoring spring force.

Abstract: A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means and an identifier means. The comparing means is configured to determine if an incoming first queue unit corresponds to the same message with a queue unit that has existed in the request storage module. The identifier setting means is configured to set a save identifier of the queue unit that has existed in the request storage module to indicate not to save a state associated with the message if the first queue unit corresponds to the same message with the queue unit that has existed in the request storage module. According to the technical solution of the invention, the access to the memory caused by saving/loading the states is reduced and thereby increases the processing speed of the processor.

Abstract: An electrical circuit for use as a string of lights in one embodiment includes a full-wave rectifier for converting an electrical source of AC into DC; and a load comprising a plurality of lamps connected in series, each of the lamps comprising an LED, a loading member in parallel with the LED, and a conductor interconnecting the LED and the loading member. The loading member is either a bidirectional Zener diode or a resistor element.

Abstract: An apparatus and method for managing a translation look-aside buffer (TLB). The TLB is shared by a plurality of jobs. The method including the steps of: obtaining at least one attribute of each job of the plurality of jobs; assigning a priority level to each job according to at least one attribute of each job; and managing the related TLB entries of each job according to the priority level of each job. The present invention also provides an apparatus for managing TLB corresponding to the above method. The method and apparatus according to the present invention provide an efficient use of the shared TLB.

Abstract: In one embodiment an electrical circuit for use as a string of lights includes a load comprising a plurality of lamps connected in series, the lamps comprising a first group of lamps including an LED and a first Zener diode in parallel therewith, and a second group of lamps including an incandescent light bulb and a second Zener diode in parallel therewith; and a rectifier for converting a source of AC into DC which is supplied to the load. The first group of lamps are alternate with the second group of lamps.

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract: A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space.

Abstract: A string of LED light is provided. The string of LED light has a full-wave rectifier with a capacitor based filter for increasing output voltage to the range of 2.6 to 2.84 times as compared with the output voltage of a typical full-wave rectifier without filter so that an increased number of lamps each having an LED and a Zener diode in parallel therewith can be attached to the string of LED light.

Abstract: An LED bulb in one embodiment includes two depending arms; a Zener diode secured to one end of one arm; an LED secured to one end of the other arm; a conductor electrically interconnecting the Zener diode and the LED; and an enclosure formed of epoxy resin with the Zener diode, the LED, the conductor, and one ends of the arms being concealed therein, wherein either a cathode of the LED is connected in series with a cathode of the Zener diode or an anode of the LED is connected in series with an anode of the Zener diode. The LED is adapted to emit red, green, or blue light.