Patents by Inventor Tao-Chih Chang

Tao-Chih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210210409
    Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 8, 2021
    Applicants: Industrial Technology Research Institute, Lite-On Semiconductor Corporation
    Inventors: Wei-Kuo Han, Chia-Yen Lee, Jing-Yao Chang, Tao-Chih Chang
  • Patent number: 11004816
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20210082810
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 18, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Publication number: 20210066257
    Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.
    Type: Application
    Filed: January 7, 2020
    Publication date: March 4, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Kuo Han, Jing-Yao Chang, Tao-Chih Chang
  • Publication number: 20210035914
    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Yu-Min Lin, Tao-Chih Chang
  • Publication number: 20210013256
    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
    Type: Application
    Filed: September 11, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Min LIN, Tao-Chih CHANG
  • Patent number: 10784297
    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 22, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Min Lin, Tao-Chih Chang
  • Patent number: 10743411
    Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 11, 2020
    Assignees: ICP Technology Co., Ltd., Industrial Technology Research Institute
    Inventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
  • Publication number: 20200245456
    Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
  • Publication number: 20200203246
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Patent number: 10672677
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 2, 2020
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, WIN-HOUSE ELECTRONIC CO., LTD.
    Inventors: Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin, Chih-Ming Tzeng, Hsiao-Ming Chang, Chih-Ming Shen
  • Patent number: 10622274
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 14, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Publication number: 20200083332
    Abstract: A semiconductor device includes a substrate, a channel layer, a first electrode layer, a second electrode layer, and a gate structure. The substrate includes a first gallium oxide layer. The channel layer is disposed on the substrate, where the channel layer is a second gallium oxide layer. The first electrode layer and the second electrode layer are disposed on the channel layer. The gate structure is disposed on the channel layer between the first electrode layer and the second electrode layer. The gate structure is on the channel layer or the gate structure has a bottom portion extending into the channel layer.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Heng Lee, Shin-Yi Huang, Tao-Chih Chang
  • Publication number: 20200075519
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 10490473
    Abstract: A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 26, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shin-Yi Huang, Yu-Min Lin, Tao-Chih Chang
  • Patent number: 10490478
    Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
  • Publication number: 20190252345
    Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 15, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20190237373
    Abstract: A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate.
    Type: Application
    Filed: April 17, 2018
    Publication date: August 1, 2019
    Inventors: Shin-Yi HUANG, Yu-Min LIN, Tao-Chih CHANG
  • Publication number: 20190206916
    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
    Type: Application
    Filed: November 19, 2018
    Publication date: July 4, 2019
    Inventors: Yu-Min LIN, Tao-Chih CHANG
  • Publication number: 20190109064
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Application
    Filed: May 11, 2018
    Publication date: April 11, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han