Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Abstract: A package unit and a stacking structure thereof are provided. The package unit includes a substrate, a first patterned circuit layer, a first conductive pillar, a semiconductor element, an insulation layer, a second conductive pillar, a third conductive pillar, a second patterned circuit layer and a conductive bump. The first patterned circuit layer is disposed on a surface of the substrate. The first conductive pillar is deposited through the substrate. The semiconductor element is disposed on the substrate. The insulation layer covers the semiconductor element and the substrate. The second conductive pillar is deposited through the insulation layer. The third conductive pillar is deposited through the insulation layer. The second patterned circuit layer is disposed on the insulation layer. The conductive bump is disposed on the second patterned metal layer.

Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Abstract: The invention provides a semiconductor device module package structure and a series connection method thereof. The semiconductor device module package structure includes a wafer having a plurality through holes. A doped layer covers a top surface of the first electrode, and inner sidewalls extending to a bottom surface of the first electrode. At least two first electrodes are disposed adjacent to each other and on opposite sides of the through holes. A second electrode covers the doped layer and the through holes. At least two insulating layer patterns overlap with the first and second electrodes. A second electrode conductive pattern is disposed on the second electrode. The second electrode conductive pattern is disposed between the insulating layer patterns, electrically connecting to the second electrode.

Abstract: A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.

Abstract: The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.

Abstract: A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.

Abstract: A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided.

Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Abstract: An artificial retina chip module including a signal processing chip, a first polymer bump layer, and a photodiode array chip is provided. The signal processing chip includes a plurality of first pad disposed on a surface thereof. The first polymer bump layer includes a plurality of polymer bumps insulated from one another. Each of the first polymer bumps is composed of a polymer material and a conductive layer coated on the polymer material. Each first polymer bump is embedded into the corresponding first pad and the signal processing chip, wherein one end of the first polymer bump protrudes from the first pad and the other end thereof protrudes from a back surface of the signal processing chip. The photodiode array chip is disposed at one side of the signal processing chip and is electrically connected to the signal processing chip through the first polymer bumps.

Abstract: A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has at least one first opening, wherein the first opening correspondingly exposes the bonding pad. The first conductive layer covers an inner wall of the first opening and the bonding pad so as to form a concave structure in the first opening. When the chip structure is bonded to a substrate, the solder bump of the substrate is inlaid into the concave structure of the chip. Moreover, a fabrication process of the chip structure, a flip chip package structure and a fabrication process thereof, a package structure of a light emitting/receiving device and a chip stacked structure are also provided.

Abstract: A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.

Abstract: A method and a device for enhancing the solderability of a lead-free component are provided. The provided method is compatible with the conventional soldering process and is capable of improving the wetting ability of the solder so as to enhance the solderability and the ability of anti-oxidation thereof. Besides, it is also achievable for providing a recognizable lead-free device so as to prevent the process confusion.

Abstract: A method and a device for enhancing the solderability of a lead-free component are provided. The provided method is compatible with the conventional soldering process and is capable of improving the wetting ability of the solder so as to enhance the solderability and the ability of anti-oxidation thereof. Besides, it is also achievable for providing a recognizable lead-free device so as to prevent the process confusion.