Patents by Inventor Tao Chu

Tao Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006734
    Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin, Yang Zhang, Chung-Hsun Lin
  • Publication number: 20250006579
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Avijit Barik, Tao Chu, Minwoo Jang, Aurelia Wang, Conor P. Puls
  • Publication number: 20240321962
    Abstract: Described herein are nanoribbon-based transistor devices in which the nanoribbons have rounded cross-sections. The nanoribbons may include caps or outer layers of semiconductor channel material grown over an inner layer of semiconductor channel material. Different materials may be used for the outer layers of NMOS and PMOS transistors. In one example, an integrated circuit device includes NMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon, and a PMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon germanium.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Robin Chao, Guowei Xu, Feng Zhang, Minwoo Jang
  • Publication number: 20240321887
    Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Yanbin Luo, Yusung Kim, Minwoo Jang, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Yang Zhang, Zheng Guo
  • Publication number: 20240321859
    Abstract: An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Anand S. Murthy, Tahir Ghani
  • Publication number: 20240321987
    Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Guowei Xu, Robin Chao, Chiao-Ti Huang, Feng Zhang, Minwoo Jang, Chia-Ching Lin, Biswajeet Guha, Yue Zhong, Anand S. Murthy
  • Publication number: 20240304619
    Abstract: An IC device includes a backside FTI separating a first transistor from a second transistor. The FTI may be between a source region of the first transistor and a drain region of the second transistor. The source region of the first transistor and the drain region of the second transistor may be different portions of a semiconductor structure, e.g., a fin or nanoribbon. The IC device may also include a frontside metal layer. The semiconductor structure may have a first surface and a second surface opposing the first surface. The first surface of the semiconductor structure may be closer to the metal layer and larger than the second surface of the semiconductor structure. The FTI may have a first surface and a second surface opposing the first surface. The first surface of the FTI may be closer to the metal layer but smaller than the second surface of the FTI.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 12, 2024
    Inventors: Guowei Xu, Chiao-Ti Huang, Robin Chao, Tao Chu, Feng Zhang, Yang Zhang, Biswajeet Guha, Oleg Golonzka
  • Publication number: 20240304621
    Abstract: Fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example fabrication method is based on patterning a foundation over which a superlattice is provided so that a single superlattice may be used to form both PMOS and NMOS stacks of nanoribbons. An example IC structure includes a support, an NMOS stack of nanoribbons stacked vertically above one another over the support, and a PMOS stack of nanoribbons stacked vertically above one another over the support, wherein at least one of the nanoribbons of the NMOS stack is vertically offset with respect to at least one of the nanoribbons of the PMOS stack.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 12, 2024
    Applicant: Intel Corporation
    Inventors: Chiao-Ti Huang, Tao Chu, Robin Chao, Guowei Xu, Feng Zhang, Biswajeet Guha, Stephen M. Cea
  • Publication number: 20240290788
    Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Applicant: Intel Corporation
    Inventors: Guowei Xu, Tao Chu, Chiao-Ti Huang, Robin Chao, David Towner, Orb Acton, Omair Saadat, Feng Zhang, Dax M. Crum, Yang Zhang, Biswajeet Guha, Oleg Golonzka, Anand S. Murthy
  • Publication number: 20240290835
    Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Applicant: Intel Corporation
    Inventors: Chiao-Ti Huang, Guowei Xu, Tao Chu, Robin Chao, Jaladhi Mehta, Brian Greene, Chung-Hsun Lin
  • Publication number: 20240282728
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Application
    Filed: May 2, 2024
    Publication date: August 22, 2024
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Publication number: 20240222484
    Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Kevin P. O'Brien, Ashish Verma Penumatcha, Chelsey Dorow, Kirby Maxey, Carl H. Naylor, Tao Chu, Guowei Xu, Uygar Avci, Feng Zhang, Ting-Hsiang Hung, Ande Kitamura, Mahmut Sami Kavrik
  • Patent number: 12027603
    Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 12002774
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Publication number: 20240178101
    Abstract: Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Tao CHU, Guowei XU, Feng ZHANG, Chiao-Ti HUANG, Minwoo JANG
  • Publication number: 20240178273
    Abstract: Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Chiao-Ti HUANG, Tao CHU, Guowei XU, Chung-Hsun LIN, Brian Greene
  • Publication number: 20240113118
    Abstract: Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul A. Packan
  • Publication number: 20240105718
    Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Guowei Xu, Minwoo Jang, Yanbin Luo, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin
  • Publication number: 20240105770
    Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Tao CHU, Guowei XU, Chia-Ching LIN, Minwoo JANG, Feng ZHANG, Ting-Hsiang HUNG
  • Publication number: 20240088217
    Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Chia-Ching Lin, Yanbin Luo, Ting-Hsiang Hung, Feng Zhang, Guowei Xu