Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: Embodiments of the disclosure provide receivers for a light detection and ranging (LiDAR) scanner. The receiver includes a photodetector configured to receive a laser beam, and convert the received laser beam to an electrical signal including a plurality of pulses. The receiver also includes an amplifier configured to amplify the electrical signal. The receiver further includes a pulse equalizer configured to sharpen the plurality of pulses in the amplified electrical signal. Each pulse is sharpened to have a narrower width and an increased amplitude.

Abstract: A method for operating a LiDAR system in an automobile that can include sending light pulses toward an object; receiving analog sensor data from an optical sensor measuring the light pulses reflected off the object; digitizing the analog sensor data using an analog to digital conversion system having a first sampling rate to generate a first set of processed sensor data and using a time to digital conversion system having a second sampling rate that is greater than the first sampling rate to generate a second set of processed sensor data; selecting the first set of processed sensor data when the analog sensor data is beneath a threshold signal to noise ratio; selecting the second set of processed sensor data when the analog sensor data exceeds the threshold signal to noise ratio; and calculating a range between the LiDAR system and the object by extracting time of flight data from the selected set of processed sensor data.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

Abstract: Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.

Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.

Abstract: A light health care system including a physiological sensing device, a processor, and a light source device is provided. The physiological sensing device is adapted to acquire physiological data of a user. The processor is coupled to the physiological sensing device, and the processor acquires at least one light parameter corresponding to the physiological data according to the physiological data. The light source device is coupled to the processor, and the light source device outputs a light beam according to the at least one light parameter, wherein a green light beam or a blue light beam in the light beam accounts for more than 40% of the light beam. A light health care method is also provided.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

Abstract: The present disclosure, in some embodiments, relates to a method of transporting a semiconductor wafer. The method includes transferring a semiconductor wafer into a first wafer slot of a second plurality of wafer slots within an adaptive inset. The adaptive inset is arranged within an interior cavity of a wafer cassette having a first plurality of wafer slots while transferring the semiconductor wafer into the first wafer slot. The wafer cassette and the adaptive inset are transported into a loading port of a semiconductor processing tool configured to perform a fabrication process on the semiconductor wafer.

Abstract: The present disclosure, in some embodiments, relates to a wafer cassette system. The wafer cassette system includes a wafer cassette includes a first plurality of wafer slots respectively having a first width. An adaptive inset is fastened to the wafer cassette in a rigid connection. The adaptive inset includes a second plurality of wafer slots respectively having a second width that is less than the first width. The second plurality of wafer slots are configured to receive a substrate after the adaptive inset has been fastened to the wafer cassette.

Abstract: One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.

Abstract: One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.

Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

Abstract: A FinFET device is provided, which includes a semiconductor substrate, a fin structure and a dielectric material. The fin structure is extending from the semiconductor substrate, the fin structure having an upper fin section, a middle fin section and a lower fin section. The dielectric material is over the semiconductor substrate embedding a first portion of the lower fin section. The dielectric material forms shallow trench isolation regions of the FinFET device.

Abstract: Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.