Patents by Inventor Tao Li

Tao Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261422
    Abstract: A semiconductor device comprises a contact electrically connected to a source/drain region of a transistor and to a gate region of the transistor. A via is disposed along a side of the contact, wherein the via comprises a conductive material. A dielectric liner layer is disposed around at least a portion of the conductive material. The dielectric liner layer electrically isolates the contact from the conductive material, and the via contacts a bit-line.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 14, 2025
    Inventors: Ruilong Xie, Carl Radens, Lawrence A. Clevenger, Huimei Zhou, Tao Li
  • Publication number: 20250261426
    Abstract: A semiconductor structure including a first backside dielectric, a second backside dielectric, and an etch stop liner sandwiched between the first backside dielectric and the second backside dielectric.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 14, 2025
    Inventors: Sagarika Mukesh, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250254945
    Abstract: A semiconductor structure is provided that includes backside S/D contact placeholder structures that have different depths. Notably, a semiconductor structure is provided that includes a deep backside S/D contact placeholder structure for high-density devices having short channel lengths and a narrow space between each of the high-density devices, and a shallow backside S/D contact placeholder structure for high-performance devices having long channel lengths and a wide space between each of the high-performance devices.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 7, 2025
    Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Shogo Mochizuki
  • Patent number: 12380057
    Abstract: Techniques for improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor are provided. The techniques include obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and a number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and improving the computing efficiency of the processor by configuring the computational size of each computing core in the processor based on the k-th parameter.
    Type: Grant
    Filed: September 25, 2024
    Date of Patent: August 5, 2025
    Assignee: Beijing Zitiao Network Technology Co., Ltd.
    Inventors: Yunfeng Shi, Hangjian Yuan, Tao Li, Jing Xing, Jian Wang
  • Patent number: 12382719
    Abstract: A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: August 5, 2025
    Assignee: International Business Machines Corporation
    Inventors: Tao Li, Ruilong Xie, Kangguo Cheng
  • Patent number: 12371981
    Abstract: The present disclosure relates to a prediction method for constant production decline of a water-producing gas well in a highly heterogeneous reservoir.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: July 29, 2025
    Assignee: Southwest Petroleum University
    Inventors: Xiaohua Tan, Daijin Zhuang, Mingqing Kui, Qian Li, Fei Zhang, Tao Li, Zhenglin Mao, Yan Zhang, Xiaoping Li, Miaofeng Cui, Xian Peng, Longxin Li, Xixiang Liu, Zihan Zhao
  • Publication number: 20250234812
    Abstract: A grafting device and a grafting method based on a UV (Ultraviolet Rays) adhesive are provided. The grafting device includes a workbench, a transfer mechanism, a seedling loading mechanism, a cutting mechanism, an adhesive spraying mechanism, a curing mechanism and a seedling unloading mechanism. Along the circumferential direction of the transfer mechanism, a seedling loading station, an adhesive spraying station, a curing station and a seedling unloading station are sequentially arranged. The seedling loading mechanism is configured for bearing a rootstock and a scion, and the cutting mechanism is configured for cutting the rootstock and the scion. The transfer mechanism is configured for receiving and fixing the rootstock and the scion, and transporting the rootstock and the scion intermittently from the seedling loading station, the adhesive spraying station, the curing station and the seedling unloading station in turn to obtain a grafted seedling.
    Type: Application
    Filed: April 17, 2024
    Publication date: July 24, 2025
    Applicant: Research Center of Intelligent Equipment, Beijing Academy of Agriculture and Forestry Sciences
    Inventors: Kai JIANG, Chunjiang ZHAO, Qingchun FENG, Liping CHEN, Tao LI, Wenqian HUANG, Qian ZHANG
  • Patent number: 12369217
    Abstract: A device disconnection processing method includes determining a disconnected smart device according to a current connection thread and a stored smart device information, determining a corresponding wireless reconnection mode based on a disconnection duration, re-establishing a wireless connection with the disconnected smart device based on the wireless reconnection mode, marking a wireless connection mode, monitoring an external network, and determining a data transmission mode based on the wireless connection mode and the external network for data transmission based on the data transmission mode with the reconnected disconnected smart device.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: July 22, 2025
    Assignee: SHENZHEN TCL NEW TECHNOLOGY CO., LTD.
    Inventors: Yunhua Wang, Tao Li
  • Publication number: 20250231812
    Abstract: A scheduling method, a scheduling apparatus, an electronic device and a storage medium are provided. The scheduling method includes: respectively performing, by a plurality of compute units, a first convolution computation on a plurality of data groups that corresponds to the plurality of compute units respectively, to obtain a plurality of first computation result groups; determining a data replication-transmission mode corresponding to the plurality of first computation result groups in the plurality of compute units, according to a configuration rule of a second convolutional layer in the plurality of compute units; and for the first compute unit that requires to perform effective data row padding among the plurality of compute units, obtaining a first intermediate data row required by the first compute unit for padding in the second convolution computation process from a first computation result group in the second compute unit, based on the data replication-transmission mode.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 17, 2025
    Inventors: Hangjian YUAN, Dongming YANG, Tao LI, Yunfeng SHI, Jian WANG
  • Patent number: 12362278
    Abstract: A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: July 15, 2025
    Assignee: International Business Machines Corporation
    Inventors: Tao Li, Ruilong Xie, David Wolpert, Albert M. Chu
  • Publication number: 20250226319
    Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level on top of a supporting structure and the metal level includes a first metal line of a first type and a second metal line of a second type, where the metal line of the first type has a first section and a second section on top of the first section, the first section includes a first type of ruthenium having a first impurity level and the second section includes a second type of ruthenium having a second impurity level, the first impurity level is lower than the second impurity level, and where the second metal line of the second type includes the first type of ruthenium and is devoid of the second type of ruthenium. A method of forming the same is also provided.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 10, 2025
    Inventors: Gideon Oyibo, Koichi Motoyama, Ruilong Xie, Tao Li, Christopher J. Penny, Hosadurga Shobha, Chanro Park, John Christopher Arnold, Kisik Choi
  • Publication number: 20250227977
    Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first source/drain (S/D) region of a first transistor and a second S/D region of a second transistor; a first backside contact metal (BCM) conductively connected to the first S/D region, the first BCM having a first longitudinal axis; and a second BCM conductively connected to the second S/D region, the second BCM having a second longitudinal axis, where the first longitudinal axis of the first BCM intersects with the second longitudinal axis of the second BCM in an acute angle. A method of forming the same is also provided.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Min Gyu Sung, Tao Li, Ruilong Xie
  • Patent number: 12355875
    Abstract: A conference data transmission method, an apparatus and a system, an electronic device and a readable medium are disclosed, belong to the technical field of computers and can avoid the illegal intrusion in the prior art. The conference data transmission method includes: receiving unencrypted first conference data transmitted by a conference transmission device in a case where an identity verification of a participant is passed; acquiring a conference key corresponding to the first conference data, and encrypting the first conference data through the conference key, to obtain encrypted second conference data; and transmitting the encrypted second conference data to the conference transmission device, so that the conference transmission device provides the encrypted second conference data to a conference client through a cloud platform. The present disclosure can improve the security of conference data transmission and avoid the problem of cracking in the data transmission process.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 8, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xitong Ma, Tao Li
  • Publication number: 20250218946
    Abstract: A semiconductor structure including first and second FET devices and a method of forming the structure. A first FET is formed with a first source/drain structure and a second FET is formed with a second source/drain structure. A via backside power rail (VBPR) metal contact structure is formed between the first FET device and the second FET device, the VBPR contact structure having a first portion contacting an underlying backside power rail and a second via portion electrically contacting only a sidewall of the first source/drain of the first FET device. The first portion of the VBPR contact structure contacting the backside power rail is of a first width and the second via portion of the VBPR contact structure contacting only a sidewall of the source or drain of the first FET device is of a second width, the first width greater than the second width.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Gideon Oyibo, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250218977
    Abstract: A semiconductor device that includes at least two chiplets separated by an insulating region. The semiconductor device further includes a through insulator via extending through the insulating region. The through insulator via includes a coaxial arrangement of a signal via having ground shielding about a perimeter of the signal via. The ground shielding is continuous from a first face of the insulating region to a second face of the insulating region.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Manasa MEDIKONDA, Tao Li, Ruilong Xie, Joshua M. Rubin
  • Publication number: 20250218941
    Abstract: A semiconductor structure extends laterally with a first interconnect on one side and a second interconnect on an opposing side separated from the first interconnect by a longitudinal thickness of an insulating member that extends laterally along the first interconnect and the second interconnect. The semiconductor structure includes a first source/drain (S/D) positioned in the insulating member between the first interconnect and the second interconnect, a second S/D positioned in the insulating member adjacent to the first S/D, and a first lead electrically connected to the first S/D and to the second interconnect and electrically insulated from the second S/D. A first lateral end of the first lead is angled inwards towards the first S/D at a first acute angle, and a second lateral end of the first lead is angled away from the first S/D at a second acute angle.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Inventors: Min Gyu Sung, Tao Li, Ruilong Xie, Chih-Chao Yang
  • Publication number: 20250219022
    Abstract: A semiconductor device comprises a wafer with an active interposer comprising one or more active components in an active component layer. The semiconductor device comprises a first chiplet that is mounted on the wafer and above the active interposer, a second chiplet that is mounted on the wafer and above the active interposer, and an interconnect layer having an interconnection that bridges between the first chiplet and the second chiplet. The interconnect layer is configured to transfer at least one of power and a signal from a bottom-side bump on a bottom side of the wafer to at least one of the first chiplet and the second chiplet, directly or indirectly, through a TSV of the active interposer.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Manasa MEDIKONDA, Tao LI, Ruilong Xie, Cheng Chi, Joshua M. Rubin
  • Publication number: 20250217677
    Abstract: A data processing method, an electronic device, and a storage medium. The data processing method is applied to a compiled neural network model, a compiled computation graph corresponding to the neural network model includes M fusion computing nodes, M is a positive integer, and the data processing method includes: packaging data in a plurality of input data groups to obtain at least one instance input data, wherein each instance input data at least includes data required by at least one of M fusion computing nodes when the neural network model executes one-time model inference; reading one instance input data of the at least one instance input data; based on the instance input data, executing an execution instruction corresponding to at least one fusion computing node, to obtain an output of the at least one fusion computing node; and outputting the output of the at least one fusion computing node.
    Type: Application
    Filed: March 21, 2025
    Publication date: July 3, 2025
    Inventors: Shuai WANG, Tao LI, Hangjian YUAN, Yunfeng SHI, Jian WANG
  • Publication number: 20250218944
    Abstract: A semiconductor structure extends laterally with a first interconnect on one side and a second interconnect on an opposing side separated from the first interconnect by a longitudinal thickness of an insulating member that extends laterally along the first interconnect and the second interconnect. The semiconductor structure includes a first source/drain positioned in the insulating member between the first interconnect and the second interconnect, a second source/drain positioned in the insulating member adjacent to the first source/drain, and a lead electrically connected to the first source/drain and to the second interconnect, wherein a portion of the lead laps the first source/drain and the second source/drain laterally and is electrically insulated from the second source/drain.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Inventors: Min Gyu Sung, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Patent number: 12349041
    Abstract: The present invention discloses an intelligent internet of things integrated perception system and method thereof, the integrated perception system comprises a data perception layer (1); a connection and transmission layer (2); an edge computation layer (3); a cloud computation layer (4); an application layer (5). The data perception layer (1) is composed of a plurality of sensor device nodes, and transmits the monitored environmental data to the edge computation layer (3) through the connection and transmission layer (2); the cloud computation layer (4) performs data fusion according to data provided by each edge computation device, and forms action instructions for the plurality of application devices.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: July 1, 2025
    Assignee: Tianjin University
    Inventors: Tie Qiu, Ning Chen, Haodong Wang, Keqiu Li, Xiaobo Zhou, Tao Li, Jiancheng Chi