Abstract: Aspects of lighting estimation, and models therefor are provided including aspects to train such models. There is provided a lighting estimation model pre-trained using synthetic data to alleviate the costs and difficulty in obtaining real portrait image and HDR environment map paired datasets. To improve model performance, the model is training utilizing a discriminator configured to predict one or more average color values of a defined percentage of highest intensity pixels of a predicted environment map and to determine a color loss associated with the predicted environment map and the one or more average color values. The trained model can be used for a wide range of downstream tasks, including being used to generate hair renderings with realistic lighting effects for virtual try on experiences.

Abstract: The present innovation unveils a non-invasive in vivo intracranial pressure (ICP) monitoring device and method relying on meningeal absorbance changes. Comprising a signal excitation module, spectral data acquisition module, and data processing module, the device incorporates a laser and optical parametric oscillator in the signal excitation module. Optical path adjustments are facilitated by concave lenses and convex lens mirrors between the laser's output and the optical parametric oscillator's input. The optical parametric oscillator's output is equipped with a coaxial lens group and a fiber bundle. This approach ensures non-invasive ICP monitoring, providing ease of use, precision, reliability, and continuous dynamic monitoring, significantly reducing patient discomfort during ICP monitoring. The method offers an objective foundation for disease diagnosis, condition assessment, and the formulation of effective diagnosis and treatment strategies, showcasing substantial clinical potential.

Abstract: A method for determining target points of heliostats during preheating of a tower-type solar photo-thermal power station comprises: establishing a coordinate system of a heliostat field of the station; obtaining coordinates of each heliostat according to a layout of the heliostat field; obtaining vertex coordinates of each heat absorbing panel on a heat absorber according to a layout of the heat absorbers; carrying out grid division for each panel to obtain vertex coordinates of each grid; obtaining X and Y coordinates of the target point of each heliostat on the panel; taking a Z coordinate of the target point of each heliostat on the panel as an independent variable and a sum of squares of differences between an actual number and an expected number of target points in each grid as an objective function to establish a non-linear optimization model, and solving the model to obtain the Z coordinate.

Abstract: Semiconductor devices include transistors in an active layer. Top vias are in electrical contact between top surfaces of the transistors and overlying frontside back-end-of-line (BEOL) layers. A local interconnect is in electrical contact between transistors underneath the transistors. Bottom vias are in electrical contact between bottom surfaces of the transistors and underlying backside BEOL layers.

Abstract: A semiconductor device includes a row of source/drain regions delineating a frontside and a backside opposite the frontside of the semiconductor device. A front gate cut from the frontside of the device has a depth that is less than a height of a gate structure for the semiconductor device. A back gate cut from the backside of the semiconductor device contacts the front gate cut.

Abstract: A semiconductor structure including a first transistor having a first gate-to-gate space and a first source drain region, a second transistor having a second gate-to-gate space and a second source drain region, where the first gate-to-gate space is less than the second gate-to-gate space, and where a bottommost surface of the first source drain region is above a bottommost surface of the second source drain region.

Abstract: Semiconductor devices include an active part that includes a semiconductor channel and a gate stack. A frontside part includes a frontside electrical contact to the active part. A backside part includes a backside electrical contact to the active part. A lower gate cap electrically insulates the gate from the backside electrical contact and includes a first region of the lower gate cap that is in contact with a shallow trench isolation (STI) structure of the backside part and a second region of the lower gate cap that is in contact with a surface of the backside electrical contact.

Abstract: A semiconductor structure includes a transistor at a first side of the semiconductor structure, a contact to the transistor at a second side of the semiconductor structure, and sidewall spacers surrounding a portion of sidewalls of the contact. The contact has a first width above the sidewall spacers and a second width below the sidewall spacers, the second width being different than the first width. The second width may be greater than the first width.

Abstract: A semiconductor device includes source/drain regions laterally disposed relative to one another in a row on a backside of the semiconductor device. A diffusion break is disposed between two adjacent source/drain regions and extends toward the backside between two source/drain region contacts. The diffusion break includes a different lateral dimension between the two adjacent source/drain regions than between the two source/drain region contacts.

Abstract: A semiconductor device including a source drain region adjacent to a nanosheet stack, a wrap around source drain contact, the wrap around source drain contact includes an upper region, a middle region and a lower region, where the upper region is above the source drain region, the middle region covers an upper horizontal surface of the source drain region and surrounds an upper portion of an angled vertical side surface of the source drain region, and the lower region surrounds a remaining portion of the angled vertical side surface of the source drain region, where a thickness of the wrap around source drain contact in the middle region is greater than a thickness of the wrap around source drain contact in the lower region.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers disposed on a substrate, a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers disposed on the substrate, a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate, and source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate.

Abstract: Techniques for providing connectivity between cloud and on-premises systems are disclosed. A computer system may receive, by a node of a virtual private cloud from a software application running on the virtual private cloud, a virtual host identification of a destination host running on an on-premises network, and identify, by the node, a virtual Internet Protocol (IP) address of the destination host based on the virtual host identification. Then, the computer system may send, by the node, a request comprising the virtual IP address of the destination host to a software agent running on the on-premises network, where the software agent is configured to send the request to the destination host using the virtual IP address.

Abstract: A paging cycle adjusting method for an electronic terminal is provided. The method includes: determining, when the electronic terminal is switched from a first service mode to a second service mode, a service requirement of the second service mode; and adjusting a paging cycle of the electronic terminal to a target paging cycle according to the service requirement of the second service mode. A computer-readable storage medium and an electronic terminal are also provided.

Abstract: A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source/drain region-gate cut dielectric layers. The lateral contact connects a via over a first source/drain region of the first transistor to a second source/drain region of the second transistor.

Abstract: A semiconductor structure is provided that has a lowered gate aspect ratio on the shallow trench isolation area to prevent gate structure flop over. The structure includes a shallow trench isolation region including a first trench dielectric material having a first height. The structure further includes an active device region located adjacent to the shallow trench isolation region. The active device region includes a second trench dielectric material having a second height which is less than the first height.

Abstract: A semiconductor device is provided. The semiconductor device includes a nanosheet stack disposed on a substrate. The semiconductor device also includes a source/drain epitaxial layer disposed on the substrate adjacent to the nanosheet stack. The semiconductor device also includes a source/drain contact formed in contact with the source/drain epitaxial layer. The source/drain contact includes a wrap-around portion that wraps around sidewall surfaces of the source/drain epitaxial layer, and an extending portion that extends from the wrap-around portion, where the wrap-around portion has a non-uniform thickness.

Abstract: A microelectronic structure including a first nanosheet transistor that includes a first source/drain. A second nanosheet transistor that is adjacent to the first nanosheet transistor and the second nanosheet transistor includes a second source/drain. A first backside contact connected to a backside surface of the first source/drain. A second backside contact connected to a backside surface of the second source/drain. A first shallow trench fill layer located between the first backside contact and the second backside contact. A second shallow trench fill layer located adjacent to the first backside contact. The second shallow trench fill layer is located on the opposite side of the first backside contact than the first shallow trench isolation layer. A backside isolation pillar located on top of the first shallow trench isolation fill layer. A top surface of the backside isolation pillar is coplanar with a top surface of the first and second backside contact.

Abstract: A resistive random access memory is provided including an asymmetrical or symmetrical bottom electrode which has an angled profile which forms an interface with a memory switching layer. The angled profile can include a slanted surface or one including a plurality of slanted surfaces that converge into a point. Bottom electrodes having such angled profiles provide more forming area, which can reduce forming voltage without area penalty. In some embodiments in which the slanted surfaces converge into a point, bottom electrodes having such an angled profile can also provide a more controlled area for the forming process to occur.

Abstract: A semiconductor device includes a first nanosheet stack on a front side of a semiconductor substrate, a second nanosheet stack on the front side of the semiconductor substrate separated from the first nanosheet stack by a source/drain region, and a deep nanosheet trench extends into the source/drain region between first and second nanosheet stacks. A source/drain is in the deep nanosheet trench and includes a bottom end having a backside source/drain divot formed therein. A deep trench liner is interposed between the deep nanosheet trench and the source/drain, the deep trench liner having an opening exposing the bottom end of the source/drain. A backside contact is on a backside of the semiconductor device, the backside contact physically contacting the exposed bottom end of the source/drain.