Abstract: A semiconductor device includes a nanosheet field effect transistor (FET), and an overlay mark adjacent to the nanosheet FET. The overlay mark includes a middle section, a first vertical spacer segment adjacent to a first end of the overlay mark, and a second vertical spacer segment adjacent to a second end of the overlay mark. The first vertical spacer segment and the second vertical spacer segment are isolated from direct contact with the middle section by a shallow trench isolation (STI).

Abstract: A semiconductor device includes a bipolar device and a logic device adjacent the bipolar device. A backside of the bipolar device is connected to a backside interconnect. A frontside of the bipolar device is connected to a back end of line (BEOL).

Abstract: A wrap-around dielectric structure prevents backside contacts shorting to gates in nanosheet field effect transistors (FETs). A method of making same includes providing a sacrificial layer under a nanosheet stack adjacent shallow trench isolation (STI) regions, recessing the STI regions' liner to from gaps in communication with the sacrificial layer, removing the sacrificial layer to form a cavity, and filling the cavity and gaps with a continuous dielectric material which wraps around a subsequently formed backside contact.

Abstract: A semiconductor structure including a single diffusion break (SDB) containing an airgap located between neighboring source/drain regions is provided. The airgap has an upper region that has a first width and a lower region that has a second width that is less than the first width. The airgap is pinched off on the backside of the structure in a region that is in close proximity to a backside interconnect structure. The presence of the airgap containing SDB can minimize capacitance as well as leakage of the structure.

Abstract: A plasma etching system includes a reaction chamber configured to react plasma with a substrate to perform an etching process, and a chamber port providing visual access to an internal area of the reaction chamber. A chamber port assembly is disposed in the chamber port and is configured to generate an electric field in response to receiving a voltage. The plasma etching system can also repel plasma ions by forming an electrically conductive transparent window-protective film on surface of a data collection window, and disposing the data collection window in a chamber port of a plasma etching system. A voltage can then be applied to the electrically conductive transparent window-protective film to generate an electric field. A plasma etching process can then be performed in the reaction chamber and the plasma ions produced during the etching process are repelled away from the data collection window via the electric field.

Abstract: Embodiments of the present disclosure are directed to processing methods and resulting structures for providing a backside placeholder dielectric fill to enable robust backside source/drain contacts. In a non-limiting embodiment, nanosheets having a first width are formed in a first region and nanosheets having a second width greater than the first width are formed in a second region. The first region includes a first S/D region and a second S/D region electrically coupled to a backside contact and a frontside contact, respectively. The second region includes a third S/D region and a fourth S/D region electrically coupled to a backside contact and a frontside contact, respectively. The method includes forming a backside placeholder having an air gap in the first region and forming a backside placeholder having a dimple in the second region.

Abstract: A semiconductor chip with at least one low-power nanosheet gate-all-around field-effect transistor with a backside contact and a high-performance nanosheet gate-all-around field-effect transistor. The low-power gate-all-around field-effect transistor has a source/drain electrically isolated from at least a bottom nanosheet channel. The high-performance gate-all-around field-effect transistor with a source/drain contacting each of the plurality of nanosheet channels. The low-power nanosheet gate-all-around field semiconductor device includes a dielectric material electrically isolating at least the bottom channel from a backside contact and the source/drain. The high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting at least the source/drain, the dielectric material, inner gate spacers, and a backside power rail.

Abstract: A semiconductor structure that includes a top source/drain (S/D) middle-of-line (MOL) contact via including a first side and a second side. The semiconductor structure also includes a first air gap located adjacent the first side of the top S/D MOL contact via, and a second air gap located adjacent the second side of the top S/D MOL contact via.

Abstract: A backside contact includes an extension region and may further include an inline region. The inline region is below a source/drain region may the extension region extends horizontally generally underneath an adjacent source/drain region. The adjacent S/D region may be connected to a frontside back end of line (BEOL) network by a frontside contact. The extension region may provide for relatively increased surface area for a backside wire of a backside BEOL network to connect thereto, which may relatively decrease the interfacial resistance therebetween and which may ease alignment and/or landing complexities of the backside wire against the backside contact. The extension region may further allow for relatively increased backside wire pitch between backside wires of the backside BEOL network, which may reduce the propensity of shorting between the backside wires.

Abstract: A semiconductor structure including a first nanosheet transistor device, a second nanosheet transistor device, a dielectric gate cut structure between and electrically isolating the first nanosheet transistor device from the second nanosheet transistor device, where a first portion of the dielectric gate cut structure has a positive tapered profile, and a second portion of the dielectric gate cut structure has a negative tapered profile.

Abstract: A microelectronic structure including a first nanosheet transistor that includes a first source/drain and a second nanosheet transistor that includes a second source/drain. The first source/drain and the second source/drain are aligned along a common axis. The common axis is parallel to a gate direction. A backside width of the first source/drain and a backside width of the second source/drain are different as measured along the common axis. A bottom dielectric isolation layer located on a backside surface of the second source/drain. A backside contact located on a backside surface of the first source/drain.

Abstract: The present disclosure provides engineered proline hydroxylase polypeptides for the production of hydroxylated compounds, polynucleotides encoding the engineered proline hydroxylases, host cells capable of expressing the engineered proline hydroxylases, and methods of using the engineered proline hydroxylases to prepare compounds useful in the production of active pharmaceutical agents.

Abstract: A semiconductor structure includes a first backside source/drain region and a second backside source/drain region in a substrate, associated with an extra gate device, disposed within a backside region of the semiconductor structure.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a standard logic cell having a top field effect transistor (FET) and a bottom FET. Further, the top FET includes multiple top channels, Additionally, the top channels are in contact with a first dielectric liner of a first gate cut region. Further, the bottom FET includes multiple bottom channels. Additionally, the bottom channels are in contact with a second dielectric liner of a second gate cut region. Further, the top FET and the bottom FET share a gate. Additionally, the top FET is disposed in an offset position with respect to the bottom FET.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for providing wrap-around backside source/drain contacts through a wafer backside. In a non-limiting embodiment, a first field effect transistor and a second filed effect transistor are formed. The first field effect transistor includes a first source or drain (S/D) region, a second S/D region, and a backside contact. The backside contact includes a lower portion and a wrap-around portion wrapping around a lower portion of the second S/D region. The second field effect transistor includes a frontside contact on a S/D region and a backside sacrificial region below the S/D region.

Abstract: A semiconductor structure including a nanosheet transistor device including a backside source drain contact, where the backside source drain contact including a top portion, a middle portion, and a bottom portion, and a dielectric liner disposed along sidewalls of the top portion of the backside source drain contact.

Abstract: A profile download method includes a primary device obtaining an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID. The primary device receives the profile download information from the mobile operator server and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and where the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: A microelectronic structure a first nanosheet transistor that includes a first source/drain, and a second nanosheet transistor that is adjacent to the first nanosheet transistor. The second nanosheet transistor includes a second source/drain. A shared gate that extends between the first nanosheet transistor and the second nanosheet transistor. A gate protrusion that extends towards a backside region of the first nanosheet transistor and the backside region of the second nanosheet transistor. A first backside contact connected to first source/drain and a second backside contact connected to the second source/drain. A signal contact connected to the gate protrusion. An isolation layer located between the signal contact and first backside contact and the isolation layer is located between the signal contact and the second backside contact.

Abstract: A condensation channel for a drying apparatus, and a drying apparatus, including two double-spiral channels which are arranged in parallel and are independent of each other. A side wall of each double-spiral channel is provided with a water-blocking structure to disperse a cooling water flow into water spray, such that not only can the side wall of the double-spiral channel be flushed by the water spray while a drying procedure is performed, but also lint in a circulating airflow can be dissolved in the water spray. A front side wall is provided with a first arc-shaped structure, a second arc-shaped structure and a flow-splitting structure. A left side wall and a right side wall of the double-spiral channel are both arc-shaped. Air entering from an air inlet is divided into two air streams by the flow-splitting structure.

Abstract: Embodiments of the present disclosure include a semiconductor structure having a transistor adjacent to a shallow trench isolation (STI) region. The STI region includes a first liner, a second liner, and fill material. The second liner is pinched off in a portion of the STI region. A backside contact is coupled to the transistor, the first liner, and the second liner.