Patents by Inventor Tao Lin

Tao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6828194
    Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: December 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tze Ho Simon Chan, Yung-Tao Lin
  • Patent number: 6822268
    Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung-Tao Lin, Sik On Kong
  • Publication number: 20040193641
    Abstract: System and methods for communicating tracking information about tagged items. A tagged item is a tangible item that carries a self-identifying tag. The tracking information can be stored in the tag or in a document that is accessible through an item tracking system. The tracking information can be accessible by multiple consumers having different levels of access. The methods include methods for masking redundancies in the tracking information, filtering the tracking information, and controlling access to the tracking information.
    Type: Application
    Filed: April 30, 2002
    Publication date: September 30, 2004
    Inventor: Tao Lin
  • Patent number: 6791576
    Abstract: Gamma correction or other power functions are generated for correcting the light intensity for digital pixels. Two levels of mapping of segments are preformed to reduce the total number of segments for a given precision. The range of inputs is divided into successively smaller segments. Each segment is smaller than the next by a factor of 1/a for a first or primary level, or 1/b for a second level of segments. All inputs are mapped or scaled up to the input range of the largest segment in the primary level. Then the largest primary segment is further divided into several second-level segments, and the input is again mapped or scaled into the largest of the second-level segments. Gamma correction is performed on the input scaled into the largest second-level segment. A linear approximation within the largest second-level segment is used.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: September 14, 2004
    Assignee: NeoMagic Corp.
    Inventor: Tao Lin
  • Patent number: 6778610
    Abstract: An error-resilient decoder for motion-picture-experts group (MPEG-4) video detects variable-length resync markers together with video packet (VP) headers at the start of each video packet in a video object plane (VOP). An f_code in the VOP header indicates a motion-vector search range and a bit length for all resync markers in the VOP. When the f_code is correctly read, the bitstream is searched for a fixed-length resync markers. However, when an error occurs in this f_code, the length of the resync markers is unknown. A multi-pattern resync marker and VP header decoder searches the bitstream for one of 7 patterns for each possible resync marker bit-length. A match allows the VP header and data to be decoded even when bit errors occur in the VOP header. Faster recovery occurs for corrupted bitstreams such as those transmitted over wireless networks.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 17, 2004
    Assignee: Redrock Semiconductor, Ltd.
    Inventor: Tao Lin
  • Publication number: 20040147689
    Abstract: A molecular composite of an industrial nylon includes a nylon having molecular chains and a poly-m-phenyleneisophthalamide (PmIA) polymerized between the molecular chains of the nylon in a copolymerization manner, thereby forming an interblock copolyamide material consisting of the molecules of the nylon and the molecules of the PmIA. Thus, the molecular composite has proper flexible elongation and tensile strength, so that it is available for various industrial products.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 29, 2004
    Inventors: Lung-Tao Lin, Ming-Fung Lin
  • Patent number: 6760258
    Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: July 6, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tze Ho Simon Chan, Yung-Tao Lin
  • Patent number: 6728318
    Abstract: A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: April 27, 2004
    Assignee: RedRock Semiconductor, Ltd.
    Inventors: Tao Lin, Stephen Molloy
  • Publication number: 20040071217
    Abstract: An MPEG decoder verifies a previous video packet by calculating the sum-of-the-absolute differences (SAD) for macroblock boundaries. When a macroblock counter goes off count, the macroblocks can be placed in the wrong relative locations in a frame. Image shapes are sliced when macroblock misplacement occurs, creating many new bisecting edges along macroblock boundaries. These image discontinuities along macroblock boundaries have a large SAD for pixels on either side of the macroblock boundary. The SAD is generated along the left and upper edges of a current macroblock, and a maximum SAD of all macroblocks in the previous video packet is generated. When the maximum SAD is above a threshold, the macroblock counter is likely to be in error, and the macroblock counter is reloaded with the header macroblock number from the next packet header. When the SAD is below threshold, a mis-matching header macroblock number is ignored.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Applicant: Luxxon Corp.
    Inventor: Tao Lin
  • Patent number: 6721000
    Abstract: An adaptive color enhancer applies different scale factors to different pixels in a digital image. More color enhancement occurs for bright pixels and for dim pixels than for average-intensity pixels. Also, more color enhancement is applied to the more colorful pixels while less color enhancement is applied to dull, less-colorful pixels. Rather than enhance all pixels to the same extent, the bright, colorful pixels are enhanced further than the average. Likewise, dim areas are color enhanced more than average. A calculation unit receives a YUV pixel. The Y value is compared to range limits and a piece-wise-linear (PWL) function generates an intermediate scale factor. The absolute values of the U and V color values are combined to create a colorfulness factor. The colorfulness factor is also used with a PWL function and the intermediate scale factor to generate a final scale factor for that pixel. The final scale factor is then multiplied by the U and V values of the pixel to generate a color-corrected pixel.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: April 13, 2004
    Assignee: NeoMagic Corp.
    Inventors: Tao Lin, Tianhua Tang
  • Patent number: 6721362
    Abstract: Error detection is added to a motion-picture-experts group (MPEG) decoder by checking each 8×8-pixel block for constraints. The constraints are added during compression by adjusting discrete cosine transform (DCT) coefficients in the block to meet a constraint. When the decoder determines that the constraint is not met by the DCT coefficients, an error is signaled for that block. The error can then be concealed using pixels from another frame or block. In one embodiment, the constraint is that the last two non-zero coefficients have the same magnitude. The constraint is added during compression after quantization but before variable-length coding by averaging the magnitudes and using the average magnitude for the last two non-zero coefficients. This minimizes visible distortion caused by the constraints and reduces computations.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 13, 2004
    Assignee: RedRock Semiconductor, Ltd.
    Inventors: Tao Lin, Stephen Molloy
  • Patent number: 6703659
    Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: March 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tze Ho Semon Chan, Yung-Tao Lin
  • Patent number: 6700934
    Abstract: Errors are detected in a motion-picture-experts group (MPEG) bitstream that has been corrupted by wireless transmission. Some 16×16 pixel macroblocks are divided into four smaller 8×8 blocks. A motion vector is encoded for each block. The Euclid distance is generated for each possible pair of the four motion vectors, and the maximum of these distances is compared to a threshold distance. When the maximum distance among the motion vectors in a macroblock exceeds the threshold, a bitstream error is signaled and error concealment is triggered. Since the four blocks within a macroblock usually stay close to each other in adjacent video frames, large jumps in the relative location of one block usually indicate a bitstream error. Squares of the distances can be generated and compared to reduce the computational load by eliminating square-root operations.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: March 2, 2004
    Assignee: Redrock Semiconductor, Ltd.
    Inventor: Tao Lin
  • Patent number: 6681990
    Abstract: Methods and apparatus, including computer program products, to support real-time inventory management. Changes to the inventory including the addition or removal of an item from the inventory are reported to the item tracking system in real-time. An inventory planner normally operates on a periodic schedule to perform inventory management functions. The inventory planner can receive alerts from an early warning agent that can cause the inventory planner to perform at least some inventory management functions, outside of its normal periodic schedule. In particular, the agent can send an alert to the inventory planner to cause the inventory planner to determine whether replenishment of store inventory is needed. To make this determination, the inventory planner can retrieve real-time inventory data from the item tracking system.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: January 27, 2004
    Assignee: SAP Aktiengesellschaft
    Inventors: Hartmut K. Vogler, Richard J. Swan, Tao Lin, James Vrieling, R. Scott Beckett, Wouter Van der Veen, Ye Chen
  • Publication number: 20030227392
    Abstract: Methods and apparatus, including computer program products, for real-time and context-aware tracking of items. Tags bound to items are read and information read from the tags and location information about the tags is provided by at least two enterprises and used to maintain disposition information about the items, which is made visible to enterprises in the supply chain. The disposition information can be mapped to a world model that tracks the items and circumstances affecting the items, for example, geo-spatial events and traffic delays. Visibility of the disposition information can be controlled through authorization. Visible information can include relationships between particular items and business documents such as order and shipping documents.
    Type: Application
    Filed: January 10, 2003
    Publication date: December 11, 2003
    Inventors: Peter S. Ebert, Richard J. Swan, Tao Lin, Jie Weng, Hartmut K. Vogler, Brian S. Mo, Stephan Haller
  • Publication number: 20030222141
    Abstract: Methods and apparatus, including computer program products, to support real-time inventory management. Changes to the inventory including the addition or removal of an item from the inventory are reported to the item tracking system in real-time. An inventory planner normally operates on a periodic schedule to perform inventory management functions. The inventory planner can receive alerts from an early warning agent that can cause the inventory planner to perform at least some inventory management functions, outside of its normal periodic schedule. In particular, the agent can send an alert to the inventory planner to cause the inventory planner to determine whether replenishment of store inventory is needed. To make this determination, the inventory planner can retrieve real-time inventory data from the item tracking system.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 4, 2003
    Inventors: Hartmut K. Vogler, Richard J. Swan, Tao Lin, James Vrieling, R. Scott Beckett, Wouter Van Der Veen, Ye Chen
  • Patent number: 6649461
    Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: November 18, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tommy Mau Lam Lai, Weining Li, Yung Tao Lin
  • Patent number: 6642962
    Abstract: A digital-camera processor receives mono-color digital pixels from an image sensor. Each mono-color pixel is red, blue, or green. The stream of pixels from the sensor has alternating green and red pixels on odd lines, and blue and green pixels on even lines in a Bayer pattern. Each mono-color pixel is white balanced by multiplying with a gain determined in a previous frame and then stored in a line buffer. A horizontal interpolator receives an array of pixels from the line buffer. The horizontal interpolator generates missing color values by interpolation within horizontal lines in the array. The intermediate results from the horizontal interpolator are stored in a column buffer, and represent one column of pixels from the line buffer. A vertical interpolator generates the final RGB value for the pixel in the middle of the column register by vertical interpolation. The RGB values are converted to YUV. The vertical interpolator also generates green values for pixels above and below the middle pixel.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: November 4, 2003
    Assignee: Neomagic Corp.
    Inventors: Tao Lin, Vincent Chor-Fung Yu, Tianhua Tang, Beong-Kwon Hwang
  • Publication number: 20030203550
    Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. A layer of pad oxide is created over the surface of a silicon substrate, a layer of silicon nitride is deposited and patterned such that the layer of pad oxide is exposed where Shallow Trench Isolation regions are to be created. A layer of photoresist is deposited, patterned and etched to expose the surface of the p-well that has been created in the surface of the substrate, p-type impurity is then implanted into the corners of the STI region that are adjacent to NMOS device that is to be created over the p-well. The process is then repeated in reverse image order to perform a n-type implant into the corners of the STI region that are adjacent to the PMOS device that is to be created over a n-well region that has been created in the surface of the substrate.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 30, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tommy Mau Lam Lai, Weining Li, Yung Tao Lin
  • Publication number: 20030203526
    Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.
    Type: Application
    Filed: May 13, 2003
    Publication date: October 30, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Yung-Tao Lin, Sik On Kong