Abstract: Digital-video compression uses motion vectors to encode movement of macroblocks from one image to another image in a sequence of images. Motion vectors are estimated using multiple levels of a picture, with higher levels having lower resolutions. Such hierarchical or pyramid motion estimation generates lower-resolution pictures from the full-resolution picture. A selected macroblock in a reference picture is compared to ranges in each successively-higher-resolution level. Rather than store the levels of a picture as full pixels, only a luminance Y component of a YUV pixel is stored and used for motion estimation. Further memory savings is achieved by reducing the width of the Y pixels from 8 bits to 6 bits for the top and bottom levels, and to 4 bits for intermediate levels of the picture. Pixels are reduced in width by storing only the most-significant-bits (MSBs), or by dithering. Motion estimation searches in each level are performed using pictures with reduced-width pixels.

Abstract: A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gatedevice including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer.

Abstract: A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer to the source/drain region to be contacted wherein the contact opening partially overlies the poly-cap layer over the adjacent gate electrode of the pair.

Abstract: A method for forming a fixing plate of a cable connector assembly comprises the steps of: providing a cable; providing a mold assembly comprising a bottom mold and a top mold, the bottom mold defining a bottom groove and a recess therein, the depth of the recess having a larger size than the diameter of the cable, the top mold defining a top groove aligned with the bottom groove and a pressing protrusion corresponding to the recess of the bottom mold; positioning the cable in the recess of the bottom mold; closing the top and bottom molds of the mold assembly, the cable being snugly retained between a bottom of the recess of the bottom mold and the pressing protrusion of the top mold; and injecting molten plastic into the top and bottom grooves of the mold assembly to form the fixing plate.

Abstract: A new method of forming non-volatile memory cells with an improved bottom silicon dioxide layer of the O—N—O has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is grown overlying the semiconductor substrate. A polysilicon layer is deposited overlying the tunneling dielectric layer. Nitrogen is implanted into the polysilicon layer to form a nitridized surface region. The polysilicon layer and the tunneling dielectric layer are then patterned to form floating gates. A bottom silicon dioxide layer is grown overlying the floating gates by thermal oxidation of the polysilicon layer. The nitridized surface region reduces the rate of thermal oxidation and creates a smooth surface. A silicon nitride layer is deposited overlying the bottom silicon dioxide layer. A top silicon dioxide layer is formed overlying the silicon nitride layer to complete the O—N—O stack.

Abstract: A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells.

Abstract: A reciprocal generator is useful for perspective correction for 3D graphics. The input range is divided into many sections. A lookup table contains reciprocal outputs for only two of the sections, the smallest-inputs section and the largest-inputs section. Entries in the table for the smallest section contain a base and a scale factor to indicate the reciprocal value. One entry is provided for each possible input value in the smallest section. This provides high precision where the outputs have the largest values, reducing visible distortions caused by relatively small changes in the large output values. Each section is divided into intervals, with one table entry for each interval. For the largest section, each table entry has an initial reciprocal and a slope of a line approximating the reciprocal curve in that interval. Reciprocals for inputs within the interval are calculated by multiplying an offset into the interval by the slope, and then adding to the initial reciprocal for that interval.

Abstract: A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by removing one net sample over many sample periods. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by adding one net sample over many sample periods.

Abstract: A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls.

Abstract: A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed.

Abstract: A new method is provided for the creation of an oxide layer that contains three different thicknesses. A first layer of oxide is grown on the surface of a substrate; a first layer of photoresist is deposited and patterned thereby partially exposing the surface of the underlying first layer of oxide. A nitrogen implant is performed into the surface of the underlying substrate; the photoresist mask of the first layer of photoresist is removed. A second layer of photoresist is deposited and patterned, the first layer of oxide is removed from above and surrounding the implanted regions of the substrate. The second mask of resist is removed.

Abstract: A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P.

Abstract: A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fog, and specular color components. The gradients for texture attributes are also generated and sent to the graphics accelerator. Both the graphics accelerator and the CPU software perform triangle edge and span walking in synchronization to each other. The CPU software walks the triangle to interpolate non-texture color and depth attributes, while the graphics accelerator walks the triangle to interpolate texture attributes. The graphics accelerator performs a non-linear perspective correction and reads a texture pixel from a texture map. The texture pixel is combined with a color pixel that is received from the CPU software interpolation of non-texture attributes.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: A video-input stream to a personal computer (PC) is converted from YUV format to RGB format. Two look-up tables are used. One look-up table has the Y and V components as address inputs, while the other look-up table has Y and U components as address inputs. The address inputs select one data word in the table for the Y,V or Y,U pair. Each data word contains an exact conversion to either the red component R or the blue component B since the result of the functions R=Y+1.371*V is stored in one table while the result of the function B=Y+1.732*U is stored in the other table. Each table also contains a partial green component in each data word. The Y,U table contains the result of the partial-green function (Y/2-0.698*V) in each data word, while the other table contains the result of the partial-green function (Y/2-0.336*U). An adder adds the two partial-green results from the two tables to produce the green component G.

Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.

Abstract: Defect scanner sensitivity and accuracy are improved for light scattering defect scanners and pattern matching defect scanners by calibrating the defect scanners to each die on a wafer using preset marks on the corresponding die. The marks have a predetermined size based on the sensitivity of the defect scanners and a predetermined position relative to the circuit pattern on the corresponding die. Alignment of the defect scanners to a specific die provides improvement in coordinate accuracy over alignment with respect to an entire wafer. A layout mapping defect filtering system collects defect scan data and determines the interaction between the detected defects and a circuit layout. The layout mapping defect filtering system provides automatic identification in real time of killer defects that cause failure of the completed integrated circuit, and classifies and analyzes defects to identify potential killer defects within specified defect classes to identify defective die.

Abstract: Audio sample rates are converted by an arbitrary ratio of Q/P using a two-stage sample-rate converter. One stage is an L-tap low-pass finite-impulse-response (FIR) filter, while the other stage is a linear interpolator. Coefficient storage for the L-tap low-pass FIR filter is dramatically reduced by reducing the effective P factor. The effective P factor is reduced by using two stages, with each stage adjusting the sampling rate by a different ratio. A first stage adjusts the sampling rate by Q0/P0, while a second stage further adjusts the sampling rate by Q1/P1. Q0 and P0 are large integers of about 400 to 700 that differ by one or three; thus the ratio Q0/P0 is very close to one. The linear interpolator stage eliminates or adds one or three samples and smoothes the samples by linear interpolation over the 400 to 700 remaining samples. The FIR filter stage adjusts the sample rate by a ratio of Q1/P1, which is approximately but not exactly Q/P.

Abstract: An audio special-effect is created by a slow phase shift. A series of all-pass digital filters are used to shift the phase of an input stream of digital-audio samples. The amount of phase shift is determined by filter coefficients. The filter coefficients are increased and decreased to sweep the phase shift up and down over a relatively long period of time such as one second per sweep. The filter coefficients must be continuously re-generated by a processor as each sweep occurs. Coefficient generation loads the processor, reducing performance of other programs and user applications. An exact prior-art method requires a division operation for each coefficient generated. Since division operations are slow, the processor is especially burdened by coefficient generation. An approximate method for coefficient generation eliminates the division operation and instead uses a multiply or a simpler shift operation.