Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

Abstract: Embodiments of the present disclosure relates to methods, systems, and apparatus for monitoring radiation output of lamps of processing chambers. In some embodiments, a system contains a plurality of lamps coupled to a chamber, and one or more radiation sensors. Each lamp is identified with one or more zones, the radiation sensors are coupled to the chamber, where each radiation sensor is proximal at least one lamp. A controller contains instructions that, when executed, cause: the radiation sensors to convey, to the controller, information associated with radiation emitted by the lamps; the controller to analyze the information, the analyzing including: for each zone: determining a function of radiation over time; and monitoring the function for a condition associated with lamp aging; and the controller to, based on the analyzing the information, perform at least one of the following: vary input power delivered to the lamps; and generate an alert.

Abstract: The present disclosure generally relates to process chambers for semiconductor processing. In one embodiment, a growth monitor for substrate processing is provided. The growth monitor includes a sensor holder and a crystal disposed in the sensor holder having a front side and a back side. An opening is formed in the sensor holder exposing a front side of the crystal. A gas inlet is disposed through the sensor holder to a plenum formed by the back side of the crystal and the sensor holder. A gas outlet is fluidly coupled to the plenum.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Abstract: A method for sidelink communication is provided. The method is applied to a first UE in a sidelink communication to transmit signals to a second UE which is a peer receiving (peer-Rx) UE of the first UE. The method includes the following steps: maintaining a counter to record how many periodic reservations remain to be used for sidelink signal transmission, wherein the periodic reservations are associated with a reservation period and each periodic reservation is associated with at least one sidelink resource; determining whether a resource re-selection condition is met before the counter counts to 0, wherein the resource re-selection condition is associated with status of receiving responses corresponding to a subset of the sidelink resources; and reselectting at least one new sidelink resource for next periodic reservations when the resource re-selection condition is met.

Abstract: A method and apparatus for calibrating a temperature within a processing chamber are described. The method includes determining an etch rate of a layer within the processing chamber. The processing chamber is a deposition chamber configured for use during semiconductor manufacturing. The etch rate is utilized to determine a temperature within the processing chamber. The temperature within the processing chamber is then subsequently compared to a calibrated temperature to determine a temperature offset. The etch rate is determined using any one of a pyrometer, a reflectometer, a camera, or a mass sensor.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.

Abstract: A display device includes: a frame, including a frame body, a first protrusion disposed on the frame body, and a second protrusion disposed on the frame body, the second protrusion including at least one stepped portion; a display panel, located on a side of one stepped portion of the at least one stepped portion close to a light emitting surface of the display device and located on an inner side of the frame body; and a planar back housing, fixed on the inner side of the frame body and a side of the first protrusion away from the light emitting surface.

Abstract: Crystalline forms of ACP-196, preparation methods, pharmaceutical compositions and uses thereof in the preparation of drugs for treatment and/or prevention of Bruton's tyrosine kinase (BTK)-mediated disorders such as autoimmune diseases or disorders, heteroimmune diseases or disorders, cancers including lymphoma and inflammatory diseases or disorders. As compared with the known solid form of ACP-196, the crystalline forms of the present invention have advantages in crystallinity.

Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

Abstract: An apparatus for heating a gas is described. The apparatus is a pre-heat ring and heater assembly positioned in a deposition chamber, such as an epitaxial deposition chamber. The pre-heat ring has a first portion configured to be heated using one or more heaters. The one or more heaters are disposed through a sidewall of the process volume beneath the pre-heat ring and are configured to heat the pre-heat ring so that gas flowed over the pre-heat ring is also heated before being flowed over a substrate. The one or more heaters may include two heaters disposed at distal ends of the first portion of the pre-heat ring. One or more temperature sensors are also configured to measure a temperature of the pre-heat ring.

Abstract: Embodiments described herein relate semiconductor manufacturing and processing. More particularly, a processing systems for auto correcting misalignments of substrates in process chambers is provided. The processing system includes a process chamber having a substrate support disposed within a chamber volume of the process chamber. The substrate support includes a pocket for receiving a substrate, and a plurality of flow conduits extending between a top surface of the pocket and a bottom surface of the substrate support. An imaging device is coupled to the process chamber and configured to monitor a position of a substrate when loaded in the pocket of the substrate support.

Abstract: An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Abstract: The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a process kit for disposition in a processing chamber applicable for use in semiconductor manufacturing includes a plate having a first face and a second face opposing the first face. The process kit includes a liner. The liner includes an annular section, and one or more ledges extending inwardly relative to the annular section. The one or more ledges are configured to support one or more outer regions of the second face of the plate. The liner includes one or more inlet openings extending to an inner surface of the annular section on a first side of the liner, and one or more outlet openings extending to the inner surface of the annular section on a second side of the liner.

Abstract: The present disclosure generally relates to process chambers for semiconductor processing. In one embodiment, a growth monitor for substrate processing is provided. The growth monitor includes a sensor holder and a crystal disposed in the sensor holder having a front side and a back side. An opening is formed in the sensor holder exposing a front side of the crystal. A gas inlet is disposed through the sensor holder to a plenum formed by the back side of the crystal and the sensor holder. A gas outlet is fluidly coupled to the plenum.

Abstract: The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide applicable for use in semiconductor manufacturing, includes a plate having a first face and a second face opposing the first face. The flow guide includes a first fin set extending from the second face, and a second fin set extending from the second face. The second fin set is spaced from the first fin set to define a flow path between the first fin set and the second fin set. The flow path has a serpentine pattern between the first fin set and the second fin set.

Abstract: The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.