Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: The present disclosure relates to processors, universal flash storage (UFS) control methods, and computer systems. One example processor includes a first processor core, a second processor core, a host controller register (HCI), and a service delivery subsystem (SDS). The HCI includes a first extended doorbell register and a second extended doorbell register. The first processor core may invoke, by using the first extended doorbell register, the HCI to provide first instruction information for the SDS, and the second processor core may invoke, by using the second extended doorbell register, the HCI to provide second instruction information for the SDS.

Abstract: The embodiments of the present invention disclose a rotating electrical machine. The rotating electrical machine comprises a stator and a rotor, the rotor comprises a rotating shaft and magnetic poles fixed to the rotating shaft, a chamfer being provided on the radial outer surface of at least one of the magnetic poles; the stator comprises a stator core, the stator core being located on one side of the magnetic poles far from the rotating shaft, the chamfer overlapping with the stator core in the axial direction of the rotor.

Abstract: Anti-tumor platinum drug mineralized protein nanoparticles and a preparation method therefor are disclosed. The anti-tumor platinum-based drug mineralized protein nanoparticles include a platinum drug and a protein. The protein is one or more selected from the group consisting of albumin, transferrin, hemoglobin, and low-density lipoprotein. The platinum drug is cisplatin, iodoplatin, bromoplatin, oxaliplatin, carboplatin, or nedaplatin. A drug loading of the anti-tumor platinum-based drug mineralized protein nanoparticles is 1% to 50%.

Abstract: The present disclosure relates to the field of microelectronic manufacturing technology, in particular to a SOT-MRAM memory cell and a method of manufacturing a SOT-MRAM memory cell. The SOT-MRAM memory cell includes a bottom electrode layer, a magnetic tunnel junction, an antiferromagnetic layer and a top electrode layer provided sequentially from bottom to top, where the magnetic tunnel junction includes a free layer, a tunneling layer and a pinning layer, the bottom electrode layer is a stack of odd number of layers, and the odd number of layers include at least one W metal layer and at least one Ta metal layer.

Abstract: A protein scaffold capable of carrying radioactive signals and application thereof in antibody detection are provided. The present disclosure successfully finds out a protein scaffold R12 capable of carrying radioactive signals, which is used for assisting part of antigens to capture corresponding antibodies; and because the method is used for carrying signals and eliminating more severe screening conditions of cross reaction in the screening process, the method is not limited to the method in application, and the method can be directly used for a technical platform which only needs to eliminate the cross reaction.

Abstract: In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.

Abstract: Disclosed are a text recognition method and apparatus, an electronic device, a storage medium, and a program product. The method includes performing a training iteration on a text recognition model based on a pre-constructed text sample set and a reference model, to obtain a trained text recognition model; and inputting text to be recognized into the trained text recognition model, and recognizing a named entity in the text to be recognized, to obtain text content corresponding to the named entity. Each training iteration comprises respectively inputting a text sample selected from the text sample set into the reference model and the text recognition model; obtaining an output difference and a prediction difference; and adjusting parameters of the text recognition model based on the output differences and the prediction difference.

Abstract: In certain aspects, a memory device includes a first semiconductor structure. The first semiconductor structure includes a vertical transistor including a semiconductor body extending in a first direction, a plurality of storage units stacked in the first direction and coupled to a first end of the vertical transistor, and a plurality of plate lines each extending perpendicularly to the first direction and coupled to a respective one of the storage units.

Abstract: The invention relates to an energy storage and driving mechanism and a nail gun having the same. The energy storage and driving mechanism includes a striking member, a driving member, and an energy storage member. Among them, the energy storage member includes a storage component, which is equipped with an inner cylinder and an outer cylinder. The outer cylinder and the inner cylinder are interconnected and form an air chamber. The striking member is movably disposed inside the inner cylinder, and has a low-energy storage position and a high-energy storage position. When the striking member is at the low-energy storage position, the volume of the air chamber is V1. When the striking member is at the high-energy storage position, the volume of the air chamber is V2. V1-V2 is approximately or equal to V2/3.

Abstract: A model optimization method includes obtaining a pre-trained model and training data including word vectors corresponding to a training text and a reference prediction result of the training text in a target service. The word vectors includes a word vector of each text word in the training text. The method further includes determining an auxiliary training parameter of a target network layer in the pre-trained model, adding the auxiliary training parameter to the target network layer to obtain a modified pre-trained model, calling the modified pre-trained model to generate target word vectors corresponding to the word vectors, respectively, performing the target service based on the target word vectors to obtain a model prediction result corresponding to the training text, and optimizing the auxiliary training parameter in a direction of reducing a difference between the model prediction result and the reference prediction result to obtain a target model.

Abstract: The present disclosure discloses a deep ultraviolet lithography method, a lithography pattern and a semiconductor structure, which relates to the field of deep ultraviolet lithography technology. The deep ultraviolet lithography method includes: dividing, when a depth of field of the deep ultraviolet lithography is less than a height of the step of the substrate, a pattern to be photoetched into at least two portions according to a distribution situation of the step, where each of the at least two portions corresponds to an on-step pattern or an off-step pattern of the step; corresponding the at least two portions of the pattern to be photoetched onto at least two masks respectively; and simultaneously baking and developing the exposed at least two masks after the at least two masks are exposed sequentially.

Abstract: An array substrate includes a gate drive circuit including shift register units in cascade. The driving method includes: in a first driving mode, loading a first clock signal with an active level and an inactive level alternating periodically to a cascade clock signal terminal of a shift register unit, and loading a second clock signal with an active level and an inactive level alternating periodically to any one of K drive clock signal terminals of the shift register unit; and in a second driving mode, loading the first clock signal to the cascade clock signal terminal, and loading a third clock signal with an active level appearing within a target time period to a target drive clock signal terminal among the K drive clock signal terminals so that a target drive output terminal corresponding to the target drive clock signal terminal outputs a gate turn-on signal.

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

Abstract: According to one aspect, an autonomous vehicle includes hardware systems which receive relatively low voltage from a low voltage power distribution unit (LVPDU). An LVPDU includes a power source such as a DC-DC converter and a plurality of backup batteries. The plurality of backup batteries is configured to provide backup power to subsets of components arranged to effectively all be powered by the power source onboard the LVPDU. The backup batteries may be tested, substantially while LVPDU is being used to provide power. The backup batteries may be charged substantially in parallel.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: The present disclosure relates to a child carrier. The child carrier includes, a seat frame, and a backrest frame. The backrest frame includes a backrest assembly capable of rotating relative to the seat frame, a headrest assembly pivotally connected to a top of the backrest assembly, a linkage side element slidably connected to the backrest assembly, and a resilient element provided between the backrest assembly and the headrest assembly. A top of the linkage side element is pivotally connected to the headrest assembly, and a bottom of the linkage side element is connected to the seat frame through a connecting belt.

Abstract: A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Abstract: The present disclosure relates to a method of obtaining a nanoscale line by using a laser, including: forming a dielectric layer and an amorphous silicon layer on a substrate sequentially; irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer, where a grain boundary of a polycrystalline silicon formed by the silicon crystallization in the partial region of the amorphous silicon layer is determined by a spacing between holes with a regular shape on the mask plate; performing a planarization process on the grain boundary of the polycrystalline silicon of the amorphous silicon layer; removing the grain boundary by using a corrosion solution to form a grain boundary trench; and obtaining the nanoscale line on the substrate by using the grain boundary trench.