Patents by Inventor Taro Osabe
Taro Osabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070257306Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.Type: ApplicationFiled: June 7, 2007Publication date: November 8, 2007Inventors: Tomoyuki Ishii, Taro Osabe, Hideaki Kurata, Takeshi Sakata
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Publication number: 20070205440Abstract: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on the floating gate interposing a second gate insulation layer therebetween, a second gate electrode which extends in the first direction and which is formed on the second charge retaining region interposing the second gate insulation layer therebetween, and a semiconductor layer which extends in a second direction and which is formed on the semiconductor substrate so as to intersect the first and the second gate electrode are provided; wherein an n-type conductive region of a second conductive type is formed on the semiconductor layer. Consequently, it achieves high-integration of a semiconductor device.Type: ApplicationFiled: December 19, 2006Publication date: September 6, 2007Inventors: Takashi Ishigaki, Taro Osabe, Takashi Kobayashi, Yutaka Imai, Masahiro Shimizu
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Publication number: 20070176219Abstract: A plurality of floating gates are formed on a principal surface of a semiconductor substrate that constitutes a nonvolatile semiconductor memory device through a first gate dielectric film. An auxiliary gate formed on the principal surface of the semiconductor substrate through a third gate dielectric film is formed on one adjacent side of the floating gates. A groove is formed on the other adjacent side of the floating gate, and an n-type diffusion layer is formed on a bottom side of the groove. A data line of the nonvolatile semiconductor memory device is constituted by an inversion layer formed on the principal surface of the semiconductor substrate to be opposed to an auxiliary gate by applying desired voltage to the auxiliary gate, and the n-type diffusion layer.Type: ApplicationFiled: December 19, 2006Publication date: August 2, 2007Inventors: Taro OSABE, Takashi Ishigaki, Yoshitaka Sasago
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Patent number: 7238570Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.Type: GrantFiled: November 14, 2005Date of Patent: July 3, 2007Assignee: Renesas Technology Corp.Inventors: Tomoyuki Ishii, Taro Osabe, Hideaki Kurata, Takeshi Sakata
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Patent number: 7078762Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.Type: GrantFiled: July 6, 2004Date of Patent: July 18, 2006Assignee: Renesas Technology Corp.Inventors: Tomoyuki Ishii, Taro Osabe, Hideaki Kurata, Takeshi Sakata
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Patent number: 7045854Abstract: An object of the present invention is to provide a semiconductor memory device suitable for larger-capacity storage because of its ability to store 3 or more bits in one element and capable of a high-speed and high-efficiency write operation due to a reduced leakage current during the write operation and provide a fabrication method therefor. According to the present invention, each of elements has a source region, a drain region, a control gate, two charge storage regions, and one or more assist gates. During a write operation, source side injection writing is performed with respect to a write target element by using the assist gates, while adjacent elements are isolated by field isolation using the assist gates.Type: GrantFiled: October 21, 2003Date of Patent: May 16, 2006Assignee: Hitachi, Ltd.Inventors: Taro Osabe, Tomoyuki Ishii, Takashi Kobayashi
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Patent number: 7045853Abstract: In a semiconductor flash memory required to have high reliability, injection and extraction of electrons must be performed through an oxide film obtained by directly oxidizing a silicon substrate. Accordingly, the voltage to be used is a large voltage ranging from positive to negative one. In contrast, by storing charges in a plurality of dispersed regions, high reliability is achieved. Based on the high reliability, transfer of electrons is permitted through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film deposited by CVD, or the like. In consequence, a device is controlled by electric potentials of the same polarity upon writing of data and upon erasing of data.Type: GrantFiled: October 5, 2004Date of Patent: May 16, 2006Assignee: Hitachi, Ltd.Inventors: Taro Osabe, Tomoyuki Ishii
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Publication number: 20060065920Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.Type: ApplicationFiled: November 14, 2005Publication date: March 30, 2006Inventors: Tomoyuki Ishii, Taro Osabe, Hideaki Kurata, Takeshi Sakata
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Publication number: 20050237786Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.Type: ApplicationFiled: June 20, 2005Publication date: October 27, 2005Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
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Patent number: 6949782Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.Type: GrantFiled: March 2, 2004Date of Patent: September 27, 2005Assignee: Hitachi, Ltd.Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
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Publication number: 20050173751Abstract: A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under ½ of the width (gate length) of the word lines.Type: ApplicationFiled: December 3, 2004Publication date: August 11, 2005Inventors: Tomoyuki Ishii, Toshiyuki Mine, Yoshitaka Sasago, Taro Osabe
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Publication number: 20050056884Abstract: In a semiconductor flash memory required to have high reliability, injection and extraction of electrons must be performed through an oxide film obtained by directly oxidizing a silicon substrate. Accordingly, the voltage to be used is a large voltage ranging from positive to negative one. In contrast, by storing charges in a plurality of dispersed regions, high reliability is achieved. Based on the high reliability, transfer of electrons is permitted through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film deposited by CVD, or the like. In consequence, a device is controlled by electric potentials of the same polarity upon writing of data and upon erasing of data.Type: ApplicationFiled: October 5, 2004Publication date: March 17, 2005Inventors: Taro Osabe, Tomoyuki Ishii
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Publication number: 20050052939Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.Type: ApplicationFiled: August 17, 2004Publication date: March 10, 2005Inventors: Taro Osabe, Tomoyuki Ishii, Kazuo Yano, Takashi Kabayashi
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Publication number: 20050029681Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.Type: ApplicationFiled: July 6, 2004Publication date: February 10, 2005Inventors: Tomoyuki Ishii, Taro Osabe, Hideaki Kurata, Takeshi Sakata
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Patent number: 6849895Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.Type: GrantFiled: September 4, 2001Date of Patent: February 1, 2005Assignee: Hitachi, Ltd.Inventors: Taro Osabe, Tomoyuki Ishii, Kazuo Yano, Takashi Kobayashi
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Patent number: 6815763Abstract: In a semiconductor flash memory required to have high reliability, injection and extraction of electrons must be performed through an oxide film obtained by directly oxidizing a silicon substrate. Accordingly, the voltage to be used is a large voltage ranging from positive to negative one. In contrast, by storing charges in a plurality of dispersed regions, high reliability is achieved. Based on the high reliability, transfer of electrons is permitted through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film deposited by CVD, or the like. In consequence, a device is controlled by electric potentials of the same polarity upon writing of data and upon erasing of data.Type: GrantFiled: February 26, 2002Date of Patent: November 9, 2004Assignee: Hitachi, Ltd.Inventors: Taro Osabe, Tomoyuki Ishii
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Patent number: 6787835Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.Type: GrantFiled: June 11, 2002Date of Patent: September 7, 2004Assignee: Hitachi, Ltd.Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
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Publication number: 20040164326Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.Type: ApplicationFiled: March 2, 2004Publication date: August 26, 2004Applicant: Hitachi, Ltd.Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
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Publication number: 20040084706Abstract: An object of the present invention is to provide a semiconductor memory device suitable for larger-capacity storage because of its ability to store 3 or more bits in one element and capable of a high-speed and high-efficiency write operation due to a reduced leakage current during the write operation and provide a fabrication method therefor. According to the present invention, each of elements has a source region, a drain region, a control gate, two charge storage regions, and one or more assist gates. During a write operation, source side injection writing is performed with respect to a write target element by using the assist gates, while adjacent elements are isolated by field isolation using the assist gates.Type: ApplicationFiled: October 21, 2003Publication date: May 6, 2004Applicant: Renesas Technology Corp.Inventors: Taro Osabe, Tomoyuki Ishii, Takashi Kobayashi
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Publication number: 20030227041Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata