Patents by Inventor Tathagata Chatterjee

Tathagata Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748818
    Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Steven Loveless, James Robert Todd, Andrew Strachan
  • Publication number: 20200203230
    Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Tathagata Chatterjee, Steven Loveless, James Robert Todd, Andrew Strachan
  • Publication number: 20200075583
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 10571511
    Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alex Paikin, Colin Johnson, Tathagata Chatterjee, Sameer Pendharkar
  • Publication number: 20190204375
    Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Yuguo WANG, Steven LOVELESS, Tathagata CHATTERJEE, Jerry DOORENBOS
  • Publication number: 20190181874
    Abstract: An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Inventors: Steven John LOVELESS, Yuguo WANG, Tathagata CHATTERJEE, Robert Stanley GRONDALSKI
  • Patent number: 10236900
    Abstract: An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven John Loveless, Yuguo Wang, Tathagata Chatterjee, Robert Stanley Grondalski
  • Publication number: 20190011493
    Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Alex PAIKIN, Colin JOHNSON, Tathagata CHATTERJEE, Sameer PENDHARKAR
  • Patent number: 10101382
    Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alex Paikin, Colin Johnson, Tathagata Chatterjee, Sameer Pendharkar
  • Publication number: 20180188313
    Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Alex PAIKIN, Colin JOHNSON, Tathagata CHATTERJEE, Sameer PENDHARKAR
  • Patent number: 9818740
    Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weidong Tian, YuGuo Wang, Tathagata Chatterjee, Rajni J. Aggarwal
  • Publication number: 20170141101
    Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.
    Type: Application
    Filed: December 5, 2016
    Publication date: May 18, 2017
    Inventors: Weidong Tian, YuGuo Wang, Tathagata Chatterjee, Rajni J. Aggarwal
  • Patent number: 9548298
    Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTUMENTS INCORPORATED
    Inventors: Weidong Tian, YuGuo Wang, Tathagata Chatterjee, Rajni J. Aggarwal
  • Patent number: 9484435
    Abstract: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Gabriel J. Gomez
  • Patent number: 9000505
    Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
  • Publication number: 20130255741
    Abstract: An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Inventors: Henry L. Edwards, Richard B. Irwin, Tathagata Chatterjee
  • Patent number: 8362462
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Publication number: 20120098590
    Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.
    Type: Application
    Filed: August 26, 2011
    Publication date: April 26, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
  • Patent number: 8134382
    Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: March 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Tathagata Chatterjee, Joseph P. Ramon, Patricia Vincent
  • Publication number: 20110253999
    Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 20, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Joseph P. Ramon, Patricia D. Vincent