Abstract: The semiconductor device includes a CPU core having functions of a control unit, an arithmetic unit, and a register; a first memory device including a plurality of blocks each including one or a plurality of rows of memory cells; a second memory device copying data that is to be treated in the CPU core from a first block selected by the CPU core from the plurality of blocks included in the first memory device, and storing the data; a plurality of switches controlling supply of power supply voltage to the respective blocks; a memory management unit recognizing an address of the first block; and a power controller turning off one of the plurality of switches using the address to stop supply of the power supply voltage to a second block of the plurality of blocks which is different from the first block.

Abstract: A microprocessor with low power consumption and a method for driving the microprocessor are provided. The microprocessor includes a processor core, a cache memory, an interrupt controller, and a power supply controller. As at least one of a plurality of memory cell arrays included in the cache memory, a memory cell array composed of a plurality of memory cells is used. At the time of switching to a low power consumption mode, data used by the processor core after supply of power is resumed is prefetched to the memory cell array; then supply of power to the cache memory is stopped. Then, the processor core fetches needed data from the memory cell array after supply of power to the cache memory is resumed.

Abstract: An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.

Abstract: A memory device includes a level shifter which includes a first input terminal, a second input terminal, a first output terminal configured to output a first signal, and a second output terminal configured to output an inverted signal of the first signal, a first buffer, a second buffer, a first node, and a second node. The first node, where an output terminal of the first buffer and the first input terminal of the level shifter are connected, is configured to hold a first data. The second node, where an output terminal of the second buffer and the second input terminal of the level shifter are connected, is configured to hold a second data.

Abstract: A passive RF tag has an advantage of being compact and lightweight. However, the driving power is limited. In order to increase the maximum communication distance and the number of objects simultaneously identified, power consumption should be efficient and reduced. The semiconductor device includes an antenna circuit, a modulation circuit electrically connected to the antenna circuit, a filter circuit electrically connected to the modulation circuit, and a logic circuit electrically connected to the filter circuit, in which the modulation circuit includes a first resistor and a transistor, the filter circuit includes a capacitor, one terminal of the first resistor is electrically connected to one of a source and a drain of the transistor, the other terminal of the first resistor is electrically connected to the antenna circuit, and a gate of the transistor is electrically connected to one terminal of the capacitor and the logic circuit.

Abstract: An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

Abstract: An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied.

Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.

Abstract: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.

Abstract: An object of the present invention is to reduce the power consumption of a modulation circuit. The modulation circuit includes a load, a diode, and a transistor. An anode of the diode is electrically connected to one terminal of an antenna via the load; a cathode of the diode is electrically connected to one of a source and a drain of the transistor; the other of the source and the drain of the transistor is electrically connected to the other terminal of the antenna; and the transistor is controlled to be turned on or off in accordance with a signal input to a gate of the transistor.

Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.

Abstract: An object is to provide a semiconductor device capable of preventing an alternating leakage current from flowing into a voltage detection circuit. The semiconductor device includes an antenna circuit, a resonance frequency regulating circuit, a voltage detection circuit, and a first capacitor. The resonance frequency regulating circuit includes a second capacitor including one terminal electrically connected to a first terminal of the antenna circuit; and a transistor including a first terminal electrically connected to the other terminal of the second capacitor, a second terminal electrically connected to a second terminal of the antenna circuit, and a gate electrically connected to the first capacitor and the voltage detection circuit.

Abstract: In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to be wrong. Note that the arithmetic portion controls transmission and reception of the instruction between the flip-flop and the memory which are included in the reading portion. This enables elimination of redundant operations in the reading portion in the case where an instruction read by the reading portion after the branch prediction turns out to be wrong is a subroutine, or the like. That is, the instruction held in the memory is transmitted back to the flip-flop without rereading of the same instruction by the reading portion, whereby the instruction can be output to the arithmetic portion.

Abstract: An object is to widen detection range of current. A current detection circuit includes a first resistor, which is connected to a first connection terminal and a second connection terminal; a second resistor, which is connected to the first resistor; a third resistor, which is connected to the first resistor; a first transistor, a source of which is connected to the second resistor; a second transistor, a source of which is connected to the third resistor, and a drain and a gate of which is connected to a gate of the first transistor; a third transistor, a source of which is connected to the source of the second transistor, and a gate of which is connected to the drain of the first transistor; and a fourth resistor, which is connected to the drain of the third transistor, and to which a voltage is input.

Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.

Abstract: An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied.

Abstract: A nonvolatile latch circuit is provided. In the latch circuit, a transistor in which a channel region is formed with an oxide semiconductor, which is a wide band gap semiconductor, is included, and data is stored in a node formed by one terminal of a capacitor and one of a source and a drain of the transistor, and is brought into a floating state when the transistor is turned off. After that, even when charge stored in the node is insufficient at time of restoring the data, charge is supplied by feedback; therefore, time necessary for restoring the data can be shortened and even when the power supply is restarted in the state of storing data, the data can be restored at high speed.

Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.