Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.

Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.

Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.

Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.

Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

Abstract: An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.

Abstract: An image processing apparatus includes an amplifying unit for, during a main scanning line period, amplifying an analog image signal input from a photoelectric conversion element and outputting the signal; an A/D converting unit for analog/digital-converting the signal to digital image data and outputting the data; and a digital offset correcting unit for performing a low-pass filter calculation based on the data to obtain an average value, calculating, based on the average value, a digital correction value used for correcting the data to obtain a desired black offset level, and performing correction on the data using the value. The digital offset correcting unit compares the value to a threshold, reduces the value to be equal to or less than the threshold if the value is equal to or greater than the threshold and updates the value to the reduced value, and performs the low-pass filter calculation and calculates the value.

Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

Abstract: According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group.

Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

Abstract: A non-volatile semiconductor memory device includes a plurality of cell units and a data writing unit. The cell unit includes first and second select gate transistors and a memory string including a plurality of memory cells. The data writing unit sequentially writes lower page data and upper page data corresponding to the lower page data to a selected memory cell selected in order from one close to the first select gate transistor to the second select gate transistor, and performs a first writing operation of writing the lower page data to the selected memory cell and a second writing operation of writing the upper page data to the selected memory cell after the first writing operation for n (n is an integer equal to or greater than 2) non-selected memory cells which are adjacent to a side of the selected memory cell close to the second select gate transistor.

Abstract: An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.

Abstract: According to one embodiment, a semiconductor device includes an active area that is formed on a semiconductor substrate, a trench that isolates the active area, a nitride film that is buried in the trench, an air gap that is formed above the nitride film along the trench, and a gate electrode that is formed on the active area to span the trench through the air gap.