Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

Abstract: An image processing apparatus includes an amplifying unit for, during a main scanning line period, amplifying an analog image signal input from a photoelectric conversion element and outputting the signal; an A/D converting unit for analog/digital-converting the signal to digital image data and outputting the data; and a digital offset correcting unit for performing a low-pass filter calculation based on the data to obtain an average value, calculating, based on the average value, a digital correction value used for correcting the data to obtain a desired black offset level, and performing correction on the data using the value. The digital offset correcting unit compares the value to a threshold, reduces the value to be equal to or less than the threshold if the value is equal to or greater than the threshold and updates the value to the reduced value, and performs the low-pass filter calculation and calculates the value.

Abstract: A semiconductor device including first and second transistors having first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface of the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom surface in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than a longitudinal direction width of the first bottom surface. A high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom surface in the longitudinal direction are larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.

Abstract: A non-volatile semiconductor memory device includes a plurality of cell units and a data writing unit. The cell unit includes first and second select gate transistors and a memory string including a plurality of memory cells. The data writing unit sequentially writes lower page data and upper page data corresponding to the lower page data to a selected memory cell selected in order from one close to the first select gate transistor to the second select gate transistor, and performs a first writing operation of writing the lower page data to the selected memory cell and a second writing operation of writing the upper page data to the selected memory cell after the first writing operation for n (n is an integer equal to or greater than 2) non-selected memory cells which are adjacent to a side of the selected memory cell close to the second select gate transistor.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a plurality of cell transistors, each of which includes a first insulating layer, a charge storage layer, a second insulating layer, and a control electrode successively provided on the substrate, side surfaces of the charge storage layer including inclined surfaces. The device further includes at least one insulator including a first insulator part provided on side surfaces of the cell transistors and on a top surface of the semiconductor substrate between the cell transistors, and a second insulator part continuously provided on an air gap between the cell transistors and on the cell transistors. A first distance from the top surface of the semiconductor substrate between the cell transistors to a bottom end of the air gap is greater than a thickness of the at least one insulator provided on the side surfaces of the cell transistors.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.

Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.

Abstract: This memory includes: bit lines; word lines crossing the bit lines; a memory cell array including memory cells provided to correspond to intersections between the bit lines and the word lines, respectively. A sense amplifier is connected to the bit lines and detects data stored in the memory cells. A word line driver controls a voltage of the word lines. An error-correcting unit includes a first error-correcting circuit having a first error-correcting capability and a second error-correcting circuit having a second error-correcting capability. The memory cells connected to each of the word lines in the memory cell block constitute a page. The error-correcting unit drives one of or both of the first and second error-correcting circuits during a data read operation or a data write operation according to a step count which is number of times of stepping up the voltage of the word lines during the data write operation.

Abstract: In the device, first and second transistors have first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface if the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than the longitudinal direction width of the first bottom. The high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom in the longitudinal direction is larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: The invention relates to a copolymer, said copolymer consisting of, as structural units, (i) 0.1 to 50 mole % of units derived from an ethylenically unsaturated monomer (a) having per one mole thereof 25 to 300 moles of C2-C3 oxyalkylene groups; (ii) 0.1 to 49.9 mole % of units derived from a monomer (b) of an alkyl, alkenyl or hydroxyalkyl ester of an ethylenically unsaturated mono- or di-carboxylic acid; (iii) 0.1 to 90 mole % units derived from a monomer (c) selected from the group consisting of an ethylenically unsaturated monocarboxylic acid, a salt thereof, an ethylenically unsaturated dicarboxylic acid, an anhydride thereof and a salt thereof; (iv) optionally up to 30 mole % of other monomers. Said copolymer can be used as a concrete and/or mortar admixture that allows optimal flow ability and, at the same time, can maintain a specific consistency, fluidity and workability of the concrete independently of the cement type.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.