Patents by Inventor Tatsuo Izumi

Tatsuo Izumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286564
    Abstract: A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 10, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yuki SAKAGUCHI, Tatsuo Izumi, Masashi Yoshida
  • Publication number: 20200098790
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
  • Patent number: 10593696
    Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
  • Patent number: 10529735
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
  • Patent number: 10510417
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuharu Yamabe, Tatsuo Izumi
  • Publication number: 20190355396
    Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Ryota SUZUKI, Tatsuo IZUMI
  • Patent number: 10431311
    Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuo Izumi, Reiko Komiya
  • Patent number: 10424348
    Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryota Suzuki, Tatsuo Izumi
  • Publication number: 20190287997
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
  • Publication number: 20190287622
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.
    Type: Application
    Filed: August 13, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuharu YAMABE, Tatsuo IZUMI
  • Publication number: 20190273093
    Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.
    Type: Application
    Filed: May 10, 2019
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuharu YAMABE, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
  • Publication number: 20190214405
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Patent number: 10332904
    Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
  • Publication number: 20190189218
    Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.
    Type: Application
    Filed: August 7, 2018
    Publication date: June 20, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuo IZUMI, Reiko KOMIYA
  • Publication number: 20190080727
    Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 14, 2019
    Inventors: Ryota SUZUKI, Tatsuo IZUMI
  • Publication number: 20180083027
    Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.
    Type: Application
    Filed: March 13, 2017
    Publication date: March 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuharu YAMABE, Ryota SUZUKI, Tatsuo IZUMI, Masahiro FUKUDA, Takuo OHASHI
  • Patent number: 9224484
    Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Izumi, Eietsu Takahashi
  • Patent number: 9070474
    Abstract: An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: June 30, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Izumi
  • Patent number: 9019581
    Abstract: An image processing apparatus includes an amplifying unit for, during a main scanning line period, amplifying an analog image signal input from a photoelectric conversion element and outputting the signal; an A/D converting unit for analog/digital-converting the signal to digital image data and outputting the data; and a digital offset correcting unit for performing a low-pass filter calculation based on the data to obtain an average value, calculating, based on the average value, a digital correction value used for correcting the data to obtain a desired black offset level, and performing correction on the data using the value. The digital offset correcting unit compares the value to a threshold, reduces the value to be equal to or less than the threshold if the value is equal to or greater than the threshold and updates the value to the reduced value, and performs the low-pass filter calculation and calculates the value.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 28, 2015
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuo Izumi, Tohru Kanno
  • Publication number: 20150023107
    Abstract: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo IZUMI, Eietsu TAKAHASHI