Patents by Inventor Tatsuo Morita

Tatsuo Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966945
    Abstract: A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 8, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Shinji Ujita, Hiroshi Inada, Tatsuo Morita
  • Patent number: 9654001
    Abstract: A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 16, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinji Ujita, Tatsuo Morita
  • Patent number: 9570435
    Abstract: A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tatsuo Morita
  • Publication number: 20160355400
    Abstract: An organic substance synthesis method according to an embodiment of the present invention is carried out using a submerged plasma device (1000), for example, and the method includes: forming a plasma through discharge in a gas including a carbon dioxide gas in contact with water; and generating an organic substance including performic acid or diformyl peroxide in the water by contact between the plasma and the water.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventor: Tatsuo MORITA
  • Publication number: 20160329890
    Abstract: A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 10, 2016
    Inventors: SHINJI UJITA, HIROSHI INADA, TATSUO MORITA
  • Patent number: 9452979
    Abstract: An organic substance synthesis method according to an embodiment of the present invention is carried out using a submerged plasma device (1000), for example, and the method includes: forming a plasma through discharge in a gas including a carbon dioxide as in contact with water; and generating an organic substance including performic acid or diformyl peroxide in the water by contact between the plasma and the water.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 27, 2016
    Assignee: PM DIMENSIONS KABUSHIKI KAISHA
    Inventor: Tatsuo Morita
  • Patent number: 9444351
    Abstract: A normally-off bidirectional switch having two gates is connected to a transformer. The transformer has a first winding and a second winding. A first gate bias power supply configured to use power generated at the first winding to supply power for driving one of the gates of the bidirectional switch and a second gate bias power supply configured to use power generated at the second winding to supply power for driving the other gate of the bidirectional switch are provided.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 13, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tatsuo Morita
  • Publication number: 20160221942
    Abstract: An organic substance synthesis method according to an embodiment of the present invention is carried out using a submerged plasma device (1000), for example, and the method includes: forming a plasma through discharge in a gas including a carbon dioxide as in contact with water; and generating an organic substance including performic acid or diformyl peroxide in the water by contact between the plasma and the water.
    Type: Application
    Filed: September 9, 2014
    Publication date: August 4, 2016
    Applicant: PM DIMENSIONS KABUSHIKI KAISHA
    Inventor: Tatsuo MORITA
  • Patent number: 9406668
    Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 2, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shuichi Nagai, Daisuke Ueda, Tatsuo Morita, Tetsuzo Ueda
  • Patent number: 9331572
    Abstract: A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi Inada, Tatsuo Morita
  • Publication number: 20160056150
    Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.
    Type: Application
    Filed: February 25, 2014
    Publication date: February 25, 2016
    Inventors: Shuichi NAGAI, Daisuke UEDA, Tatsuo MORITA, Tetsuzo UEDA
  • Publication number: 20160043643
    Abstract: A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: SHINJI UJITA, TATSUO MORITA
  • Publication number: 20150287713
    Abstract: A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventor: TATSUO MORITA
  • Publication number: 20150014746
    Abstract: A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Hiroshi INADA, Tatsuo MORITA
  • Publication number: 20140177308
    Abstract: A normally-off bidirectional switch having two gates is connected to a transformer. The transformer has a first winding and a second winding. A first gate bias power supply configured to use power generated at the first winding to supply power for driving one of the gates of the bidirectional switch and a second gate bias power supply configured to use power generated at the second winding to supply power for driving the other gate of the bidirectional switch are provided.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Tatsuo MORITA
  • Patent number: 8742467
    Abstract: A bidirectional switching device includes a semiconductor multilayer structure made of a nitride semiconductor, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor multilayer structure, and a first gate electrode and a second gate electrode. The first gate electrode is covered with a first shield electrode having a potential substantially equal to that of the first ohmic electrode. The second gate electrode is covered with the second shield electrode having a potential substantially equal to that of the second ohmic electrode. An end of the first shield electrode is positioned between the first gate electrode and the second gate electrode, and an end of the second shield electrode is positioned between the second gate electrode and the first gate electrode.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 3, 2014
    Assignee: Panasonic Corporation
    Inventors: Tatsuo Morita, Daisuke Ueda, Yasuhiro Uemoto, Tetsuzo Ueda
  • Patent number: 8604512
    Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer. The semiconductor element includes a first ohmic electrode and a second ohmic electrode, and a first gate electrode and a second gate electrode, which are sequentially formed on the first ohmic electrode between the first ohmic electrode and the second ohmic electrode. The substrate potential stabilizer sets a potential of the substrate lower than higher one of a potential of the first ohmic electrode or a potential of the second ohmic electrode.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: December 10, 2013
    Assignee: Panasonic Corporation
    Inventor: Tatsuo Morita
  • Patent number: 8569843
    Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 29, 2013
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
  • Patent number: 8497581
    Abstract: A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Ayanori Ikoshi, Yasuhiro Uemoto, Manabu Yanagihara, Tatsuo Morita
  • Patent number: RE45989
    Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 26, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Tatsuo Morita, Manabu Yanagihara, Hidetoshi Ishida, Yasuhiro Uemoto, Hiroaki Ueno, Tsuyoshi Tanaka, Daisuke Ueda