Patents by Inventor Tatsuo Nakayama
Tatsuo Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9530879Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.Type: GrantFiled: November 20, 2015Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
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Patent number: 9520489Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.Type: GrantFiled: January 26, 2015Date of Patent: December 13, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
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Patent number: 9508842Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with a gate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: GrantFiled: December 6, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Tatsuo Nakayama
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Patent number: 9502551Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.Type: GrantFiled: August 18, 2015Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
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Publication number: 20160293709Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.Type: ApplicationFiled: March 22, 2016Publication date: October 6, 2016Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO
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Publication number: 20160240648Abstract: A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape.Type: ApplicationFiled: April 29, 2016Publication date: August 18, 2016Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE
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Publication number: 20160204243Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.Type: ApplicationFiled: March 24, 2016Publication date: July 14, 2016Inventors: Takashi INOUE, Toshiyuki TAKEWAKI, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Hironobu MIYAMOTO
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Publication number: 20160172474Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with a gate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: ApplicationFiled: December 6, 2015Publication date: June 16, 2016Inventors: Shinichi MIYAKE, Tatsuo NAKAYAMA
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Patent number: 9368609Abstract: A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel.Type: GrantFiled: July 16, 2014Date of Patent: June 14, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue
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Publication number: 20160133715Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Applicant: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
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Patent number: 9337325Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.Type: GrantFiled: March 28, 2014Date of Patent: May 10, 2016Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
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Patent number: 9306027Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.Type: GrantFiled: November 20, 2014Date of Patent: April 5, 2016Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
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Patent number: 9306051Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.Type: GrantFiled: January 6, 2015Date of Patent: April 5, 2016Assignee: Renesas Electronics CorporationInventors: Yoshinao Miura, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
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Publication number: 20160079409Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Applicant: Renesas Electronics CorporationInventors: Yasuhiro OKAMOTO, Yuji ANDO, Tatsuo NAKAYAMA, Takashi INOUE, Kazuki OTA
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Publication number: 20160064538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Patent number: 9269803Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.Type: GrantFiled: July 9, 2013Date of Patent: February 23, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
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Publication number: 20160005846Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.Type: ApplicationFiled: August 18, 2015Publication date: January 7, 2016Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
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Patent number: 9231096Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.Type: GrantFiled: November 21, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
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Patent number: 9123739Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.Type: GrantFiled: July 12, 2012Date of Patent: September 1, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
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Publication number: 20150221757Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.Type: ApplicationFiled: January 26, 2015Publication date: August 6, 2015Inventors: Tatsuo NAKAYAMA, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue