Patents by Inventor Tatsuya Honda

Tatsuya Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210257498
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: April 13, 2021
    Publication date: August 19, 2021
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Patent number: 11049977
    Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 29, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Tatsuya Honda
  • Publication number: 20210184041
    Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
    Type: Application
    Filed: February 2, 2021
    Publication date: June 17, 2021
    Inventors: Shunpei YAMAZAKI, Masahiro TAKAHASHI, Tatsuya HONDA, Takehisa HATANO
  • Publication number: 20210159345
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Kengo AKIMOTO, Hiroki OHARA, Tatsuya HONDA, Takatsugu OMATA, Yusuke NONAKA, Masahiro TAKAHASHI, Akiharu MIYANAGA
  • Patent number: 10991829
    Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tatsuya Honda, Takehisa Hatano
  • Patent number: 10916663
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Publication number: 20200243686
    Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: Shunpei YAMAZAKI, Motoki NAKASHIMA, Tatsuya HONDA
  • Publication number: 20200212223
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Publication number: 20200194593
    Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.
    Type: Application
    Filed: December 31, 2019
    Publication date: June 18, 2020
    Inventors: Shunpei YAMAZAKI, Masahiko HAYAKAWA, Tatsuya HONDA
  • Patent number: 10622485
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: April 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10535776
    Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: January 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Tatsuya Honda
  • Patent number: 10468536
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10457705
    Abstract: A carrier for ligand immobilization obtained by shrinking polysaccharide porous beads not less than 10% by a shrinkage rate defined by the following formula, and crosslinking the polysaccharide porous beads: Shrinkage rate (%)=(1?V2/V1)×100 (wherein, V1 indicates the gel volume of polysaccharide porous beads before shrinkage, and V2 indicates the gel volume of polysaccharide porous beads after shrinkage).
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 29, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Takahiro Okubo, Yoshikazu Kawai, Masaru Hirano, Fuminori Konoike, Keiichi Karasugi, Tatsuya Honda
  • Publication number: 20190326444
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Kengo AKIMOTO, Tatsuya HONDA, Norihito SONE
  • Publication number: 20190256555
    Abstract: A carrier for ligand immobilization obtained by shrinking polysaccharide porous beads not less than 10% by a shrinkage rate defined by the following formula, and crosslinking the polysaccharide porous beads: Shrinkage rate (%)=(1?V2/V1)×100 (wherein, V1 indicates the gel volume of polysaccharide porous beads before shrinkage, and V2 indicates the gel volume of polysaccharide porous beads after shrinkage).
    Type: Application
    Filed: December 20, 2018
    Publication date: August 22, 2019
    Applicant: KANEKA CORPORATION
    Inventors: Takahiro OKUBO, Yoshikazu KAWAI, Masaru HIRANO, Fuminori KONOIKE, Keiichi KARASUGI, Tatsuya HONDA
  • Publication number: 20190237585
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: April 11, 2019
    Publication date: August 1, 2019
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Patent number: 10304962
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 10290744
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10221211
    Abstract: A process for producing porous cellulose beads of the present invention is characterized by comprising the steps of: a) mixing an alkali aqueous solution and cellulose to prepare cellulose micro dispersion at low temperature, b) adding water to the cellulose micro dispersion to prepare cellulose slurry, and d) bringing the cellulose slurry into contact with coagulation solvent. A carrier for ligand immobilization of the present invention is characterized by being by shrinking polysaccharide porous beads not less than 10% by a shrinkage rate defined by the following formula, and crosslinking the polysaccharide porous beads: Shrinkage rate (%)=(1?V2/V1)×100 (wherein, V1 indicates the gel volume of polysaccharide porous beads before shrinkage, and V2 indicates the gel volume of polysaccharide porous beads after shrinkage).
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 5, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Takahiro Okubo, Yoshikazu Kawai, Masaru Hirano, Fuminori Konoike, Keiichi Karasugi, Tatsuya Honda
  • Publication number: 20190054179
    Abstract: This pharmaceutical composition contains a hvdroxamic acid derivative, or a salt thereof, and a solubilizer, said hydroxamic acid derivative being selected from among (2S)-2-((4-((4-((1S)-1,2-dihydroxyethyl)phenyl)ethynyl)benzoyl)(methyl)amino)-N-hydroxy-N?,2- dimethylmalonamide, (2S)-2-((4((4-((1R)-1,2-dihydroxyethyl)phenyl)ethynyl)benzoyl)(methyl)amino)-N-hydroxy-N?,2-dimethylmalonamide, and (2S)-N-hydroxy-2-((4-((4-((1S)-1-hydroxy-2-methoxyethyl)phenyl)ethynyl)benzoyl)(methyl)amino)-N?,2-dimethylmalonamide. The pharmaceutical composition demonstrates strong antibacterial activity, has excellent solubility in water, and is useful as a drug.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Applicant: TOYAMA CHEMICAL CO., LTD.
    Inventors: Tatsuya HONDA, Yuko SUZUMURA, Tomoya KATO, Yu KOSEKI, Kohei ONO