Patents by Inventor Tatsuya Nagata

Tatsuya Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070222338
    Abstract: In an ultrasonic transducer including a gap between an upper electrode and a lower electrode on a silicon substrate, it is made possible to reduce or adjust warpage of an above-gap membrane vibrated by electrostatic actuation due to internal stress. A fourth insulating film and a fifth insulating film of films positioned above the gap which is a cavity required for transmitting and receiving ultrasonic are respectively a silicon oxide film for compression stress and a silicon nitride film for tensile stress. Therefore, compression stress and tensile stress cancel each other, so that warpage of the above-gap membrane is reduced. An amount of warpage can be adjusted by adjusting a film thickness of the fourth insulating film and a film thickness of the fifth insulating film.
    Type: Application
    Filed: January 23, 2007
    Publication date: September 27, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Takanori Aono, Tatsuya Nagata, Hiroyuki Enomoto, Shuntaro Machida
  • Patent number: 7226150
    Abstract: An inkjet head is provided and includes: a chamber substrate for forming an ink flow passage; a diaphragm substrate including a diaphragm for pressurizing a pressure chamber disposed in the chamber substrate; and a nozzle substrate for jetting ink pressurized by the diaphragm, wherein the diaphragm substrate is made of silicon, the diaphragm is made of a material selected from the group of silicon oxide film and metal film, and the diaphragm is formed in the diaphragm substrate. A method of manufacturing the inkjet head is also provided.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: June 5, 2007
    Assignees: Hitachi, Ltd., Ricoh Printing Systems Co., Ltd.
    Inventors: Yasuhiro Yoshimura, Jun Nagata, Osamu Machida, Tatsuya Nagata
  • Publication number: 20070057603
    Abstract: In a semiconductor diaphragm type electro-acoustic transducer device having no necessity for a DC bias voltage applied as a result of a charge-stored layer being provide between electrodes, electro-mechanical conversion efficiency undergoes a change owing to time-dependent change in a quantity of stored electricity due to leakage of charge, and so forth. As for sensitivity of signal reception, provided by an ultrasonic array-transducer made up of the electro-acoustic transducer devices each as a basic unit, not only a main beam sensitivity undergoes drift as a result of drift in the electromechanical conversion efficiency, but also there result deterioration in an acoustic S/N ratio, and deterioration in directionality of an ultrasonic beam.
    Type: Application
    Filed: July 24, 2006
    Publication date: March 15, 2007
    Inventors: Takashi Azuma, Shin-ichiro Umemura, Tatsuya Nagata, Hiroshi Fukuda, Shuntaro Machida, Toshiyuki Mine
  • Publication number: 20070052093
    Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.
    Type: Application
    Filed: July 20, 2006
    Publication date: March 8, 2007
    Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
  • Publication number: 20070029923
    Abstract: A display panel excellent in reduction in weight and excellent in reliability is provided. The display panel of the invention includes a cover member having a peripheral part bonded and secured to a back surface of a cathode panel, and a central part enclosed by the peripheral part which central part is joined to a reinforcing panel. The reinforcing panel is pressed against a peripheral part of the cathode panel via a support frame by atmospheric pressure exerted on the cover member.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 8, 2007
    Inventors: Atsushi Kazama, Tatsuya Nagata, Takaaki Kitada, Takashi Naitou, Yuichi Sawai
  • Publication number: 20070021024
    Abstract: There is provided a method of manufacturing a display panel and an anode panel for improving reliability of a sealing portion of the display panel. Vacuuming (evacuation of air) is performed to inside of a cavity formed by a cathode panel and an anode panel in a state of viscosity in which a sealant melts and deforms in manufacturing of a display.
    Type: Application
    Filed: July 19, 2006
    Publication date: January 25, 2007
    Inventors: Atsushi Kazawa, Tatsuya Nagata, Takaaki Kitada, Shigemi Hirasawa, Takashi Naitou, Keiichi Kanazawa
  • Publication number: 20060284519
    Abstract: The present invention aims to stabilize sound-electricity conversion characteristics of a diaphragm-type sound-electricity conversion device as well as to decrease the noise level of an ultrasonic diagnostic apparatus using the sound-electricity conversion device. The sound-electricity conversion device is configured by a capacitor cell including a lower electrode formed on a silicon substrate and an upper electrode over the lower electrode, the lower and upper electrodes sandwiching a cavity. An electrode short-circuit prevention film is formed on the upper electrode on the cavity side. The electrode short-circuit prevention film is formed of a material with an electrical time constant shorter than 1 second and longer than 10 microseconds, such as silicon nitride containing a stoichiometrically excessive amount of silicon.
    Type: Application
    Filed: January 30, 2006
    Publication date: December 21, 2006
    Inventors: Shinichiro Umemura, Takashi Azuma, Tatsuya Nagata, Hiroshi Fukuda, Toshiyuki Mine, Syuntaro Machida
  • Patent number: 7151319
    Abstract: A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: December 19, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Iida, Tatsuya Nagata, Seiji Miyamoto, Toshihiro Matsunaga
  • Publication number: 20060238100
    Abstract: The present invention has an object to provide a flat panel display which employs a high-strength glass material to realize a reduction in thickness and weight. The flat panel display includes two substrates SUB1 and SUB2 and a light emitter PMG provided between the two substrates. At least one of the two substrates is made of glass material containing SiO2 as its main component and 1 to 20 wt % of at least one selected from La, Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
    Type: Application
    Filed: April 11, 2006
    Publication date: October 26, 2006
    Inventors: Motoyuki Miyata, Osamu Shiono, Yuichi Sawai, Takashi Naitou, Tatsuya Nagata, Keiich Kanazawa, Nobuhiko Hosotani, Yuichi Inoue, Hiroshi Ito
  • Patent number: 7035081
    Abstract: The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 25, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Nagata, Seiji Miyamoto, Hideko Ando
  • Patent number: 7018857
    Abstract: A manufacturing method for improving the yield in a semiconductor manufacturing process and reducing the manufacturing cost produces a semiconductor device that is inexpensively manufactured and has a high reliability by reliably making contact during inspection with a suitable pressing force, while limiting damage to an electrode pad even when many inspected electrodes are inspected. A substrate used for inspection of the semiconductor device has a beam, a probe on the beam having a projecting shape for coming in contact with an electrode (electrode pad) of the semiconductor device, and a secondary electrode electrically connected to the probe through an electrically conductive member disposed on the side of the beam opposed to the side where the probe is provided. In an inspecting process, an inspecting device having a layer having many projections formed in the probe come in contact with the electrode pad of the semiconductor device.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: March 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Kanamaru, Takanori Aono, Tatsuya Nagata, Kenji Kawakami, Hideyuki Aoki
  • Publication number: 20060024555
    Abstract: According to the present invention, there is provided a membrane electrode composite module including a membrane electrode composite formed by sandwiching both surfaces of an electrolyte membrane between gas diffusion electrodes, an anode current collecting plate having fuel flow holes through which fuel flows, and a cathode current collecting plate having oxygen flow holes through which oxygen flows, wherein both surfaces of the membrane electrode composite are sandwiched between the anode current collecting plate and the cathode current collecting plate, the membrane electrode composite module further including films made of a synthetic resin (a first film and a second film) which are a base of the anode current collecting plate and a base of the cathode current collecting plate.
    Type: Application
    Filed: July 8, 2005
    Publication date: February 2, 2006
    Inventors: Ryuji Kohno, Tatsuya Nagata, Makoto Kitano, Masahiro Seido, Kazuhiko Nakagawa
  • Publication number: 20060003219
    Abstract: It is an object of the present invention to provide a fuel cell having a pressurizing mechanism which can optimize pressure applied to a membrane electrode assembly (MEA) working as a power-generating element to realize high-efficiency power generation and an electronic device equipped with the same. The fuel cell 10A comprises the membrane electrode assembly module 20 which consumes the liquid fuel 40 to generate power, and the fuel chamber 30 for supplying the liquid fuel 40 which it holds inside to the membrane electrode assembly module 20 from the aperture 31, wherein it is provided with the pressurizing member 60 on the membrane electrode assembly module 20, clamping member 53 for fixing the pressurizing member 60 and fuel chamber 30, and elastic member for applying a pressure on the membrane electrode assembly module 20 in its thickness direction, to solve the problems.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 5, 2006
    Inventors: Ryuji Kohno, Tatsuya Nagata, Makoto Kitano
  • Publication number: 20060003196
    Abstract: It is an object of the present invention to provide a fuel cell which can supply a liquid fuel, without changing its composition, to every corner of the membrane electrode assemblies arranged two- dimensionally over a wide area, to generate power at a high efficiency. The fuel cell 10A comprises the membrane electrode assembly modules 20 which consume the liquid fuel 40 to generate power, and the fuel chamber 30 which holds the liquid fuel 40 inside and has the principal plane on which the membrane electrode assembly modules 20 are arranged, wherein the fuel chamber 30 is provided with the fuel injection hole 33 inside, through which the liquid fuel 40 is supplied under pressure from the outside, and the fuel supply gear 42 inside, which is located to come close to the membrane electrode assembly modules 20, the fuel supply gear 42 being provided, on the surface, with the fine pores 43 through which the liquid fuel 40 can pass.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 5, 2006
    Inventors: Ryuji Kohno, Tatsuya Nagata, Makoto Kitano
  • Patent number: 6977514
    Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: December 20, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
  • Publication number: 20050270758
    Abstract: In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 8, 2005
    Applicants: NEC Corporation, Renesas Eastern Japan Semiconductor, Inc., Elpida Memory, Inc.
    Inventors: Masaharu Imazato, Atsushi Nakamura, Takayuki Watanabe, Kensuke Tsuneda, Mitsuaki Katagiri, Hiroya Shimizu, Tatsuya Nagata
  • Publication number: 20050258735
    Abstract: An object of the present invention is to achieve high resolution, lightening, and thinning of a display apparatus. The display apparatus includes an anode substrate, a planar cathode substrate forming an electron emitting chamber vacuously sealed between the cathode substrate and the anode substrate, electron sources formed on the cathode substrate, phosphors formed on the anode substrate, and a vacuum seal member forming a pressure balancing chamber on the back of the electron emitting chamber side of the cathode substrate. The vacuum seal member is placed covering the back of the electron emitting chamber side, and has a shell structure for receiving the atmospheric pressure.
    Type: Application
    Filed: May 19, 2005
    Publication date: November 24, 2005
    Inventors: Takeshi Terasaki, Atsushi Kazama, Makoto Kitano, Tatsuya Nagata, Takashi Fujimura
  • Publication number: 20050258736
    Abstract: To achieve high resolution, lightening, and thinning in a display apparatus, the display apparatus includes a thin display panel and a control unit. The display panel includes an anode substrate, a cathode substrate forming an electron emitting chamber vacuously sealed between itself and the anode substrate, phosphors formed on the anode substrate, and a pressure support formed on the back of the electron emitting chamber side of the cathode substrate. The pressure support includes a vacuum seal member forming a pressure supporting chamber vacuously sealed between itself and the cathode substrate independently of the electron emitting chamber, and a reinforcement member which is formed of a member having a gap, which is sandwiched between the vacuum seal member and cathode substrate in the pressure supporting member, and at least both end portions of which span a bonding area of the cathode substrate for the anode substrate.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 24, 2005
    Inventors: Atsushi Kazama, Takeshi Terasaki, Makoto Kitano, Tatsuya Nagata, Takashi Fujimura
  • Patent number: 6885208
    Abstract: A semiconductor device includes a quadrangular semiconductor substrate and a self test circuit formed on the semiconductor substrate. A plurality of pads are formed on the semiconductor substrate, which pads are coupled at least to the self test circuit. The semiconductor substrate includes four rectangular or square regions which each include a respective corner of the quadrangle, and at least two of the pads are respectively located on diagonally opposite ones of the regions from one another.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 26, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Miyatake, Tatsuya Nagata, Hiroya Shimizu, Ryuji Kohno, Hideyuki Aoki
  • Publication number: 20050074910
    Abstract: A manufacturing method for improving the yield in a semiconductor manufacturing process and reducing the manufacturing cost produces a semiconductor device that is inexpensively manufactured and has a high reliability by reliably making contact during inspection with a suitable pressing force, while limiting damage to an electrode pad even when many inspected electrodes are inspected. A substrate used for inspection of the semiconductor device has a beam, a probe on the beam having a projecting shape for coming in contact with an electrode (electrode pad) of the semiconductor device, and a secondary electrode electrically connected to the probe through an electrically conductive member disposed on the side of the beam opposed to the side where the probe is provided. In an inspecting process, an inspecting device having a layer having many projections formed in the probe come in contact with the electrode pad of the semiconductor device.
    Type: Application
    Filed: June 12, 2003
    Publication date: April 7, 2005
    Inventors: Masatoshi Kanamaru, Takanori Aono, Tatsuya Nagata, Kenji Kawakami, Hideyuki Aoki