Abstract: In an apparatus for measuring thickness of a thin film, which is formed through a conductor, preventing the measurement from an error due to the curve or bend on a substrate surface or a moving surface of a stage, but without necessity of a large-scaled facility, an electric filed is applied between a probe 10 and a stage 8, so as to obtain an electrostatic capacitance of the substrate 3, an electrostatic capacitance of an insulating film, which is formed between the substrate 3, and an electrostatic capacitance defined starting from the substrate 3 to the thin film 4. The electrostatic capacitance between the substrate 3 and the thin film 4 is measured at plural numbers of places covering over the entire surface of the thin film 4. The probe 10 is so supported that the contact load “P” comes to be constant, by the probe 10 onto the thin film 4. A contact area of the probe 10 between the thin film 4 is calculated out through a predetermined equation, assuming the load “P” is constant.

Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

Abstract: A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.

Abstract: The disclosure is concerned with an inkjet head comprising; a chamber substrate for forming an ink flow passage; a diaphragm substrate including a diaphragm for pressurizing a pressure chamber disposed in the chamber substrate; and a nozzle substrate for jetting ink pressurized by the diaphragm, wherein the diaphragm substrate is made of silicon, the diaphragm is made of a material selected from the group of silicon oxide film and metal film, and the diaphragm is formed in the diaphragm substrate. The disclosure is also directed to a method of manufacturing the inkjet head.

Abstract: The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise.

Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.

Abstract: BF2 for a channel stop is ion-implanted in a P-type silicon substrate, and a trench is defined in an area of the ion-implanted silicon substrate by etching. An intensity of light emission at a wavelength of 660 m when fluorine corresponding to a constituent element of BF2 is alienated, is detected to thereby sense an endpoint of the etching, whereby a device isolation trench with a channel stop region formed therebelow is formed.

Abstract: The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.

Abstract: Realized is a semiconductor device that test can be effectively conducted by the test device even where the semiconductor device is reduced in chip size and hence pad pitch. A plurality of pads are formed on both ends of a semiconductor substrate. An input pad group is arranged at a left end side of the semiconductor device while an input/output pad groups are arranged at a right end side thereof. A BIST circuit is arranged at an upper right area of the semiconductor device, and the pads close to the BIST circuit serve as BIST exclusive pads. Because the area for arranging the pads for BIST is limited due to the increase of input pads and the like and all the pads for BIST cannot be arranged at one end of the semiconductor device, the BIST pads are separately provided in both ends of the semiconductor substrate. Those close to the BIST circuit are provided as exclusive pads while the others are as common-use pads. The pads 3a and 3b are separated to the upper and lower areas of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.

Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

Abstract: The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.

Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.

Abstract: A communication route monitoring system monitors a communication route in an ATM network with OAM loopback cells. The communication route monitoring system has a first OAM loopback cell delivering unit disposed in one of the communication devices which performs a network management function, a first returning and relaying unit disposed in each of the communication devices, and a communication route recognizing unit disposed in the communication device which performs the network management function. The first OAM loopback cell delivering unit delivers a first OAM loopback cell for confirming a communication route to a route terminal point. The first returning and relaying means returns the first OAM loopback cell upon reception of the first OAM loopback cell, together with its own location identification added thereto, to a source, and relays the received first OAM loopback cell to a next one of the communication devices.

Abstract: In an ATM switch, after a communication path is properly set up, a continuity test is performed by passing an OAM cell through the communication path before initiating the transmission of user cells. After the transmission of user cells is initiated, a loopback test is performed by periodically inserting an OAM cell in a user cell flow. When a fault condition is detected as a result of the OAM cell loopback test, a peak cell rate environment is created by adding OAM cells to the user cells for a limited period of time, and communication quality is measured under the thus created environment. When a point-to-multipoint connection with a plurality of leaf points is set up, correspondence between each leaf point and a physical connection point is recorded in a table.

Abstract: In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.

Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.

Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.

Abstract: An object of the present invention is to provide a facsimile apparatus having a high resolution image display unit and a hard copying unit, which is capable of preventing wasteful consumption of recording paper sheets while revealing a reduced size and excellent operation facility.