Patents by Inventor Tatsuya Okamoto
Tatsuya Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190370201Abstract: A control unit makes a connection state between a connection device connected to a connection management device and an electronic device when a determination unit determines that identification information of the connection device connected to the connection management device has been registered in a connection work plan and a connection history of a connection order preceding a connection order of the connection device is “connected”, and does not make the connection state between the connection device connected to the connection management device and the electronic device when it is determined that the connection history of the connection order preceding the connection order of the connection device is “unconnected”.Type: ApplicationFiled: May 15, 2019Publication date: December 5, 2019Inventors: Tatsuya OKAMOTO, Takayuki KAMEDA, Ryuutarou TOMOZAWA
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Publication number: 20190225744Abstract: Provided are an active ester resin composition capable of both exhibiting low shrinkage during curing and forming a cured product having a low elastic modulus under high temperature conditions; a curable resin composition including the ester resin composition; a cured product of the curable resin composition; a printed wiring board; and a semiconductor encapsulating material. The active ester resin composition includes an active ester compound (A) that is an esterification product of a naphthol compound (a1) and an aromatic polycarboxylic acid or an acid halide thereof (a2); and an active ester resin (B) including a product of reaction of essential raw materials including a compound (b1) having one phenolic hydroxyl group, a compound (b2) having two or more phenolic hydroxy groups, and an aromatic polycarboxylic acid or an acid halide thereof (b3), in which the content of the active ester compound (A) is 40% or more.Type: ApplicationFiled: June 22, 2017Publication date: July 25, 2019Inventors: Akito Kawasaki, Yutaka Satou, Tatsuya Okamoto
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Publication number: 20190181150Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.Type: ApplicationFiled: February 5, 2019Publication date: June 13, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Wataru SAKAMOTO, Ryota SUZUKI, Tatsuya OKAMOTO, Tatsuya KATO, Fumitaka ARAI
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Publication number: 20190172768Abstract: Provided are an active ester resin capable of having low cure shrinkage and forming a cured product having a low dielectric loss tangent, a curable resin composition including the ester resin, a cured product of the resin composition, a printed wiring board, and a semiconductor encapsulating material. The active ester resin includes a product of reaction of essential raw materials including: a phenolic hydroxyl group-containing compound (A); a polynaphthol resin (B) having a molecular structure in which naphthol compound (b) moieties are linked with an aromatic ring- or cyclo ring-containing structural moiety (?); and an aromatic polycarboxylic acid or an acid halide thereof (C). Also provided are a curable resin composition including the ester resin, a cured product of the resin composition, a printed wiring board, and a semiconductor encapsulating material.Type: ApplicationFiled: June 22, 2017Publication date: June 6, 2019Applicant: DIC CorporationInventors: Yutaka Satou, Tatsuya Okamoto, Akito Kawasaki
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Publication number: 20190169424Abstract: Provided are a curable composition capable of both exhibiting a low shrinkage percentage during curing and forming a cured product having a low elastic modulus under high temperature conditions, a cured product of the curable composition, and a semiconductor encapsulating material and a printed wiring board which are produced using the curable composition. The curable composition includes an active ester compound (A) that is an esterification product of a phenolic compound (a1) and an aromatic polycarboxylic acid or an acid halide thereof (a2); and a curing agent. Also provided are a cured product of the curable composition, and a semiconductor encapsulating material and a printed wiring board which are produced using the curable composition.Type: ApplicationFiled: June 22, 2017Publication date: June 6, 2019Applicant: DIC CorporationInventors: Yutaka Satou, Akito Kawasaki, Tatsuya Okamoto
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Patent number: 10304851Abstract: A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.Type: GrantFiled: March 1, 2018Date of Patent: May 28, 2019Assignee: Toshiba Memory CorporationInventors: Hiroshi Nakaki, Yosuke Mitsuno, Tatsuya Okamoto
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Publication number: 20190153215Abstract: Provided are an active ester composition capable of exhibiting high curability and forming a cured product with various excellent properties such as low dielectric properties, a cured product thereof, and a semiconductor encapsulating material and a printed wiring board which are obtained using the active ester composition. The active ester composition includes, as essential components, an active ester compound (A) and a phenolic hydroxyl group-containing compound (B), in which the active ester compound (A) is an esterification product of a compound having one phenolic hydroxyl group in the molecular structure (a1) and an aromatic polycarboxylic acid or an acid halide thereof (a2). Also provided are a cured product thereof, and a semiconductor encapsulating material and a printed wiring board which are obtained using the active ester composition.Type: ApplicationFiled: June 22, 2017Publication date: May 23, 2019Applicant: DIC CorporationInventors: Yutaka Satou, Akito Kawasaki, Tatsuya Okamoto, Kazuhisa Yamoto
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Patent number: 10242992Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.Type: GrantFiled: July 8, 2016Date of Patent: March 26, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
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Publication number: 20190081064Abstract: A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.Type: ApplicationFiled: March 1, 2018Publication date: March 14, 2019Inventors: Hiroshi NAKAKI, Yosuke MITSUNO, Tatsuya OKAMOTO
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Patent number: 10181477Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.Type: GrantFiled: September 12, 2016Date of Patent: January 15, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hirokazu Ishigaki, Tatsuya Okamoto, Masao Shingu
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Publication number: 20180327541Abstract: Provided are a thermosetting resin composition whose cured product exhibits a low dielectric constant and a low loss tangent as well as excellent flame retardancy, heat resistance, and thermal decomposition resistance, a cured product obtained from the thermosetting resin composition, and an active ester resin for use in the thermosetting resin composition.Type: ApplicationFiled: November 10, 2015Publication date: November 15, 2018Applicant: DIC CorporationInventors: Kazuo Arita, Tatsuya Okamoto
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Patent number: 9929205Abstract: The imaging device includes a sensor substrate, a light-blocking substrate, a light-collecting substrate, a sealing material, and a light-transmitting member. The light-transmitting member includes a light-transmitting base disposed to be in contact with either the sensor substrate or the light-blocking substrate, and a light-transmitting resin which is filled between the base and the sensor substrate or the light-blocking substrate. A void is formed in at least a part of a space between the sealing material and the light-transmitting member.Type: GrantFiled: September 28, 2015Date of Patent: March 27, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Takefumi Fukagawa, Takashi Miyata, Satoshi Higuchi, Tatsuya Okamoto
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Patent number: 9842856Abstract: According to an embodiment, a semiconductor memory device comprises: a plurality of control gate electrodes stacked above a substrate; a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes; a gate insulating layer extending in the first direction and provided between the control gate electrode and first semiconductor layer; and a second semiconductor layer positioned downwardly of the first semiconductor layer and gate insulating layer, and connected to a lower end of the first semiconductor layer and the substrate. Moreover, the first semiconductor layer comprises: a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and a second portion connected to an upper end of the first portion, extending in the first direction, and having a different crystalline structure from the first portion.Type: GrantFiled: August 30, 2016Date of Patent: December 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuya Okamoto, Tatsufumi Hamada
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Publication number: 20170320994Abstract: A triazine ring-containing phenol resin obtained by reacting melamine, para-alkylphenol, and formalin is used to provide an epoxy resin composition capable of providing a cured product with excellent flame retardancy, excellent dielectric characteristics such as a low dielectric tangent and a low dielectric constant, and excellent thermal conductivity, a cured product thereof, and a prepreg, a circuit board, a build-up film, a build-up board, a semiconductor sealing material, a semiconductor device, a fiber reinforced composite material, and a formed article using the epoxy resin composition.Type: ApplicationFiled: September 24, 2015Publication date: November 9, 2017Applicant: DIC CORPORATIONInventors: Kazuo Arita, Tatsuya Okamoto, Kazuhisa Yamoto, Yutaka Sato
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Publication number: 20170263626Abstract: According to an embodiment, a semiconductor memory device comprises: a plurality of control gate electrodes stacked above a substrate; a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes; a gate insulating layer extending in the first direction and provided between the control gate electrode and first semiconductor layer; and a second semiconductor layer positioned downwardly of the first semiconductor layer and gate insulating layer, and connected to a lower end of the first semiconductor layer and the substrate. Moreover, the first semiconductor layer comprises: a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and a second portion connected to an upper end of the first portion, extending in the first direction, and having a different crystalline structure from the first portion.Type: ApplicationFiled: August 30, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuya OKAMOTO, Tatsufumi HAMADA
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Publication number: 20170263633Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.Type: ApplicationFiled: September 12, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hirokazu ISHIGAKI, Tatsuya Okamoto, Masao Shingu
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Patent number: 9754954Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: GrantFiled: July 5, 2016Date of Patent: September 5, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
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Patent number: 9698389Abstract: A method of producing an organic EL device includes forming an organic EL element including a pixel electrode, a functional layer, and a counter electrode over a substrate, forming a cathode protective layer over the organic EL element, forming a cover layer over the cathode protective layer, forming an organic buffer layer over the cover layer, and forming a gas barrier layer over the organic buffer layer.Type: GrantFiled: February 10, 2016Date of Patent: July 4, 2017Assignee: SEIKO EPSON CORPORATIONInventors: Tatsuya Okamoto, Takefumi Fukagawa
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Publication number: 20160322373Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAKAMOTO, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
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Publication number: 20160315092Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.Type: ApplicationFiled: July 5, 2016Publication date: October 27, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO