Patents by Inventor Tatsuyuki Saito

Tatsuyuki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6815330
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Publication number: 20040207095
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Application
    Filed: May 13, 2004
    Publication date: October 21, 2004
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Patent number: 6797609
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Patent number: 6797606
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Publication number: 20040180534
    Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 16, 2004
    Inventors: Junji Noguchi, Naohumi Ohashi, Tatsuyuki Saito
  • Publication number: 20040173906
    Abstract: In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower, one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 9, 2004
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Patent number: 6764945
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: July 20, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Patent number: 6764950
    Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: July 20, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naohumi Ohashi, Tatsuyuki Saito
  • Patent number: 6756679
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: June 29, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Patent number: 6731007
    Abstract: In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Patent number: 6716749
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: April 6, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
  • Publication number: 20030214043
    Abstract: Provided is a semiconductor device comprising a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect, said interconnect having a first conductor film, a second conductor film formed via the first conductor film by chemical vapor deposition or ALS and comprised of any one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor films and having copper as a main component.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 20, 2003
    Inventors: Toshio Saitoh, Kensuke Ishikawa, Hiroshi Ashihara, Tatsuyuki Saito
  • Publication number: 20030109129
    Abstract: A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.
    Type: Application
    Filed: December 27, 2002
    Publication date: June 12, 2003
    Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20030102565
    Abstract: In a manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 5, 2003
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20030089928
    Abstract: Provided is a semiconductor device comprising a first interlayer insulating film formed over a semiconductor substrate and having a wiring trench; a wiring portion which has a first barrier metal layer formed over the side walls and bottom surface of said wiring trench, a first conductor layer formed over said first barrier metal layer so as to embed said wiring trench with said first conductor layer, and a capping barrier metal film formed over the surface of said first conductor layer; a second interlayer insulating film formed over said first interlayer insulating film and having a connecting hole; and a connecting portion which has a second barrier metal layer formed over the side walls and bottom surface of said connecting hole, and a second conductor layer formed over said second barrier metal layer so as to embed said connecting hole with said second conductor layer; wherein at a joint between said connecting portion and said wiring portion, at least either one of said second barrier metal layer or sai
    Type: Application
    Filed: November 15, 2002
    Publication date: May 15, 2003
    Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20030067079
    Abstract: Provided are a manufacturing method of a semiconductor integrated circuit device, which comprises forming an interconnect trench and a contact hole in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, forming a barrier film inside of the trench and hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, forming a copper film over the barrier film, and forming the second-level interconnect and a connector portion (plug) by polishing by CMP; and the semiconductor integrated circuit device manufactured by this method.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 10, 2003
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20030045086
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hiruzu Yamaguchi, Nobuo Owada
  • Publication number: 20030017692
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Publication number: 20030001183
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 2, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
  • Publication number: 20030001280
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 2, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada