Patents by Inventor Tatsuyuki Saito

Tatsuyuki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110290182
    Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Inventors: Masanori SAKAI, Yukinao Kaga, Takashi Yokogawa, Tatsuyuki Saito
  • Patent number: 8053893
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwaskai, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20110198954
    Abstract: Disclosed is a motor in which a commutator (10) is provided with connecting wires which short-circuit equipotential segments; brushes (21) are constituted by a low-speed brush (21a), a high-speed brush (21b), and a common brush (21c) used in common by the low-speed and high-speed brushes, and are juxtaposed along the circumferential direction. The circumferential brush width (W2) of the high-speed brush is set to be smaller than the circumferential brush width (W1) of the low-speed brush. The high-speed brush and the low-speed brush are formed so that simultaneous sliding contact with equipotential segments (15) can be avoided. Additionally, armature cores (8) are provided such that a plurality of teeth (12) is point-symmetrical about a rotary shaft (3) at equal intervals in the circumferential direction, and the teeth and slots (13) are formed so as to exist alternately at intervals of 90 degrees in the circumferential direction.
    Type: Application
    Filed: October 7, 2009
    Publication date: August 18, 2011
    Inventors: Tatsuyuki Saito, Ryuichi Takakusagi, Toshiyuki Kimura, Yoshichika Kawashima, Kenji Sakata
  • Publication number: 20110186984
    Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which are able to form a conductive film, which is dense, includes a low concentration of source-derived impurities and has low resistivity, at a higher film-forming rate. The substrate processing apparatus includes a processing chamber configured to stack and accommodate a plurality of substrates; a first processing gas supply system configured to supply a first processing gas into the processing chamber; a second processing gas supply system configured to supply a second processing gas into the processing chamber; and a control unit configured to control the first processing gas supply system and the second processing gas supply system.
    Type: Application
    Filed: January 26, 2011
    Publication date: August 4, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsuyuki SAITO, Masanori SAKAI, Yukinao KAGA, Takashi YOKOGAWA
  • Publication number: 20110183519
    Abstract: A method of manufacturing a semiconductor device and a substrate processing apparatus capable of providing a TiN film that is higher in quality than a TiN film formed by a conventional CVD method at a higher film-forming rate, that is, with a higher productivity than a TiN film formed by an ALD method.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 28, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinao KAGA, Tatsuyuki SAITO, Masanori SAKAI, Takashi YOKOGAWA
  • Patent number: 7948088
    Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: May 24, 2011
    Assignees: Hitachi, Ltd., Honda Motor Co., Ltd.
    Inventors: Toshio Saito, Satoshi Moriya, Morio Nakamura, Goichi Yokoyama, Tatsuyuki Saito, Nobuaki Miyakawa
  • Publication number: 20110059600
    Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 10, 2011
    Applicant: HITACHI-KOKUSAI ELECTRIC INC.
    Inventors: Masanori SAKAI, Yukinao KAGA, Takashi YOKOGAWA, Tatsuyuki SAITO
  • Publication number: 20110031593
    Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 10, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Tatsuyuki SAITO, Masanori SAKAI, Yukinao KAGA, Takashi Yokogawa
  • Publication number: 20100304567
    Abstract: A TiN film is formed by a first step of forming a TiN intermediate film on a wafer by supplying TiCl4 and NH3 reacting with TiCl4 to the wafer and controlling a processing condition for causing a bonding branch that has not undergone a substitution reaction to remain at a predetermined concentration at a part of TiCl4 and a second step of substituting the bonding branch contained in the TiN intermediate film by supplying H2 to the wafer, the first step and the second step being performed in this order.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masanori SAKAI, Tatsuyuki SAITO
  • Publication number: 20100297846
    Abstract: A method of manufacturing a semiconductor device includes the steps of: forming a first metal film on the substrate placed in a processing chamber by alternately supplying at least one type of a metal compound that is an inorganic raw material and a reactant gas that has reactivity to the metal compound to the processing chamber more than once; forming a second metal film on the substrate by simultaneously supplying at least one type of a metal compound that is an inorganic raw material and a reactant gas that has reactivity to the metal compound to the processing chamber once so that the metal compound and the reactant gas are mixed with each other; and modifying at least one of the first metal film and the second metal film is modified using at least one of the reactant gas and an inert gas after at least one of the alternate supply process and the simultaneous supply process.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 25, 2010
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinao Kaga, Tatsuyuki Saito, Masanori Sakai
  • Patent number: 7777343
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: August 17, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 7777346
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 17, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Patent number: 7642652
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 5, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20090256261
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 7569476
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20090174080
    Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
    Type: Application
    Filed: August 25, 2006
    Publication date: July 9, 2009
    Inventors: Toshio Saito, Satoshi Moriya, Morio Nakamura, Goichi Yokoyama, Tatsuyuki Saito, Nobuaki Miyakawa
  • Publication number: 20090115063
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 7, 2009
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20080230916
    Abstract: A semiconductor IC device includes a buried interconnection in interconnection layers over a semiconductor substrate, in which electrical connection of interconnections are provided over and under an interconnection layer of an embedded interconnection from among the interconnection layers such that a first connecting conductor portion within a connecting hole extending from an upper interconnection toward the interconnection layer of a predetermined buried interconnection and a second connecting conductor portion within the connecting hole extending from a lower interconnection toward the interconnection layer of the predetermined buried interconnection are electrically connected via a connecting conductor portion for relay in the connecting groove of the interconnection layer of a predetermined buried interconnection.
    Type: Application
    Filed: May 23, 2008
    Publication date: September 25, 2008
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Patent number: 7387957
    Abstract: In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers formed, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: June 17, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Publication number: 20080138979
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: January 23, 2008
    Publication date: June 12, 2008
    Inventors: Junji NOGUCHI, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada