Abstract: In some aspects, an integrated circuit comprises an input voltage terminal, a capacitor terminal, a first NMOS transistor connected to the input voltage terminal, a first PMOS transistor connected to a first NMOS gate terminal of the first NMOS transistor and connected to the capacitor terminal, the first PMOS transistor having a first PMOS gate terminal, a second PMOS transistor connected to the first NMOS gate terminal of the first NMOS transistor, the second PMOS transistor having a second PMOS gate terminal, a switched output terminal, a second NMOS transistor connected to the switched output terminal, a third NMOS transistor connected to the switched output terminal, an inverter, and a complementary metal oxide semiconductor (CMOS) transistor pair, the CMOS transistor pair having an input connected to the third NMOS transistor and an output connected to a second PMOS gate terminal of the second PMOS transistor.

Abstract: In some examples, an apparatus comprises: an amplifier having an amplifier output and first and second amplifier inputs, the first amplifier input coupled to a reference voltage terminal, and the second amplifier input coupled to a power input terminal; a ramp generation circuit having a reset input and a ramp output; a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the amplifier output, and the second comparator input coupled to the ramp output; and a switching signal generation circuit having a circuit input and a circuit output, the circuit input coupled to the comparator output, and the circuit output coupled to a power control terminal.

Abstract: In some examples, a switch-mode power supply circuit comprises a pulse generation circuit comprising an oscillator, the oscillator configured to generate first pulses using a fixed frequency regulation for a first load condition that exceeds a predefined threshold and configured to generate second pulses using a variable frequency regulation for a second load condition that does not exceed the predefined threshold. The circuit also includes a power converter coupled to the pulse generation circuit and configured to convert a first voltage to a regulated voltage using either one of the first or second pulses generated by the pulse generation circuit. The circuit further comprises an output filter coupled to the power converter and configured to produce a second voltage from the regulated voltage.

Abstract: A saturation detection system determines when a first transistor device enters or is in saturation. The system includes a comparator block coupled between an input voltage rail and a bootstrapped voltage rail, and the first transistor is coupled between the input voltage rail and a switching node terminal. A second transistor device is coupled to an output of the comparator block and is used to signal when the first transistor device enters saturation. One or more transistor devices within the comparator block switch off when the voltage across the drain and source terminals of the first transistor device becomes higher than a saturation threshold. When this happens, the output of the second transistor device may be toggled, which can be detected using sensing logic. The saturation detection system may have particular usefulness in voltage regulators that use switching element to sense inductor current, such as buck and/or boost converters.

Abstract: In some examples, a switch-mode power supply circuit comprises a pulse generation circuit comprising an oscillator, the oscillator configured to generate first pulses using a fixed frequency regulation for a first load condition that exceeds a predefined threshold and configured to generate second pulses using a variable frequency regulation for a second load condition that does not exceed the predefined threshold. The circuit also includes a power converter coupled to the pulse generation circuit and configured to convert a first voltage to a regulated voltage using either one of the first or second pulses generated by the pulse generation circuit. The circuit further comprises an output filter coupled to the power converter and configured to produce a second voltage from the regulated voltage.

Abstract: Described embodiments include a circuit for voltage regulator startup. The circuit includes a voltage regulation circuit having first and second regulator inputs and a regulator output. A startup circuit has a startup input coupled to the first regulator input, and a startup output. A reference generation circuit has first and second reference inputs and first and second reference outputs. The first reference input is coupled to the regulator output. The second reference input is coupled to the startup output, and the first reference output is coupled to a reference output terminal and to the second regulator input. A reference detection circuit has a first detection input coupled to the regulator output, and a second detection input coupled to the second reference output, and provides a reference ready signal responsive to a reference voltage being within a reference specification.

Abstract: A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.

Abstract: A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.

Abstract: Described embodiments include a circuit for voltage regulator startup. The circuit includes a voltage regulation circuit having first and second regulator inputs and a regulator output. A startup circuit has a startup input coupled to the first regulator input, and a startup output. A reference generation circuit has first and second reference inputs and first and second reference outputs. The first reference input is coupled to the regulator output. The second reference input is coupled to the startup output, and the first reference output is coupled to a reference output terminal and to the second regulator input. A reference detection circuit has a first detection input coupled to the regulator output, and a second detection input coupled to the second reference output, and provides a reference ready signal responsive to a reference voltage being within a reference specification.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

Abstract: In some examples, an apparatus comprises: an amplifier having an amplifier output and first and second amplifier inputs, the first amplifier input coupled to a reference voltage terminal, and the second amplifier input coupled to a power input terminal; a ramp generation circuit having a reset input and a ramp output; a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the amplifier output, and the second comparator input coupled to the ramp output; and a switching signal generation circuit having a circuit input and a circuit output, the circuit input coupled to the comparator output, and the circuit output coupled to a power control terminal.

Abstract: A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.

Abstract: A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.

Abstract: A system includes: an input voltage source; a power stage coupled to the input voltage source; a load coupled to an output of the power stage; and an error amplifier circuit coupled to the power stage. The error amplifier circuit includes an error amplifier; a transconductance stage coupled to an output of the error amplifier; an internal compensation switch; an external compensation switch; and control logic coupled to the internal compensation switch and the external compensation switch. The control logic is configured to selectively operate the internal compensation switch and the external compensation switch in one of an internal compensation mode and an external compensation mode.

Abstract: A circuit is configured to drive a switch mode regulator and to control the slew rate at a switching terminal of the regulator. The circuit includes first and second transistors coupled between a voltage supply terminal and a switching terminal, and includes third and fourth transistors coupled between the voltage supply terminal and the switching terminal. The circuit includes a fifth transistor coupled to the fourth transistor in a current mirror configuration and a sixth transistor coupled between the voltage supply terminal and the third transistor. The circuit includes a first resistor coupled between the voltage supply terminal and the fifth transistor, and includes a second resistor coupled between the sixth transistor and the second transistor.

Abstract: A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.

Abstract: In some examples, a switch-mode power supply circuit comprises a pulse generation circuit comprising an oscillator, the oscillator configured to generate first pulses using a fixed frequency regulation for a first load condition that exceeds a predefined threshold and configured to generate second pulses using a variable frequency regulation for a second load condition that does not exceed the predefined threshold. The circuit also includes a power converter coupled to the pulse generation circuit and configured to convert a first voltage to a regulated voltage using either one of the first or second pulses generated by the pulse generation circuit. The circuit further comprises an output filter coupled to the power converter and configured to produce a second voltage from the regulated voltage.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

Abstract: In some examples, a switch-mode power supply circuit comprises a pulse generation circuit comprising an oscillator, the oscillator configured to generate first pulses using a fixed frequency regulation for a first load condition that exceeds a predefined threshold and configured to generate second pulses using a variable frequency regulation for a second load condition that does not exceed the predefined threshold. The circuit also includes a power converter coupled to the pulse generation circuit and configured to convert a first voltage to a regulated voltage using either one of the first or second pulses generated by the pulse generation circuit. The circuit further comprises an output filter coupled to the power converter and configured to produce a second voltage from the regulated voltage.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.