Abstract: A system and a method are disclosed for providing a temperature compensated under-voltage-lockout circuit that has a trip point voltage that is not sensitive to temperature variation. The under-voltage-lockout circuit of the invention comprises (1) an inverter circuit that is coupled to a supply voltage and (2) a temperature compensation circuit that is coupled to the supply voltage and to the inverter circuit. The temperature compensation circuit and the inverter circuit temperature compensate a trip point voltage of the inverter circuit by driving an input of the inverter circuit with a voltage that has a same temperature coefficient as the trip point voltage of the inverter circuit.

Abstract: A multi-phase regulator that provides a smooth transition between DCM and CCM by employing partially synchronous rectification in which a duty cycle of a synchronous switch enable signal is gradually increased to 100%. The regulator includes a separate inductor, high-side switch, and synchronous switch for each phase. The high-side switches are controlled based on a separate PWM signal for each phase. Each PWM signal is provided by pulse width modulating the error signal, with each of the PWM signals having a different phase. During the partially synchronous rectification, the synchronous switch turns on when the high-side switch is off and the synchronous switch enable signal is asserted, and the synchronous switch is off otherwise. The synchronous switch enable signal has a frequency relative to the frequency of each of the pulse width modulation output signal such that good current sharing among the inductors of each phase is achieved.

Abstract: A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is arranged to track a low limit voltage Vlo and a lowest voltage Vvalley. The offset voltage is one half of a difference between Vlo and Vvalley. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phase 1 and phase 2. The sample-and-hold circuit provides Vlo and Vvalley to a differential amplifier that is arranged to provide the offset voltage to a hysteretic controller circuit. In one embodiment, the offset voltage is added to a reference voltage for corrected output voltage. In another embodiment, the offset voltage is added to the output voltage.

Abstract: A method and circuit for compensating offset errors caused by propagation delays in hysteretic control loops. An overshoot voltage VOS, caused mainly by an inductor current overshoot, is tracked and held when a switch is to be turned off, and again when the switch actually turns off. A timing logic circuit provides control signals to a sample and hold circuit based on switch signals SW and OUT. A difference between the two sampled voltages is applied to a reference voltage in a hysteretic voltage regulator. By monitoring the overshoot voltage and automatically compensating for it in real-time, a knowledge of a value of the propagation delay is not needed. Thus, significantly improved accuracy may be achieved despite variable factors such as propagation delay variations, temperature changes, component tolerances, and the like.