Abstract: A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: A semiconductor device includes: a first well region in a substrate; at least one isolation region arranged in the substrate and defining an anode area, a cathode area and a bulk area of a Schottky diode device in the first well region; a first dielectric layer over the first well region; and a conductive layer over the first well region, the conductive layer forming a Schottky barrier interface, of the Schottky diode device, with the first well region. The first dielectric layer includes: a first portion including a first thickness; a second portion including a second thickness less than the first thickness and laterally surrounded by the first portion; and a sidewall arranged directly over one of the at least one isolation region and connecting the first portion and the second portion.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

Abstract: A method of manufacturing a Schottky barrier diode includes: forming a first well region and a second well region adjacent to the first well region in a substrate; depositing a first dielectric layer over the first well region and the second well region; performing a first patterning operation on the first dielectric layer to cause the first dielectric layer to include a stepped shape; performing a second patterning operation on the first dielectric layer to form a gate dielectric layer of a first transistor device in the second well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface.

Abstract: A method for forming an integrated circuit includes following operations. A substrate is received. The substrate includes a first region, a second region and an isolation structure. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed on a portion of the first top surface, a top of the second top surface and the boundary. A dielectric structures is formed over the substrate. Top surfaces of the dielectric structure, the first device, the second device and the dummy structure are aligned with each other. A first metal gate is formed in the first device, and a second metal gate is formed in the second device.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A method for manufacturing a semiconductor device includes forming a first CPODE dummy poly gate and a second CPODE dummy poly gate on a semiconductor substrate; removing the first CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a first trench extending into the semiconductor substrate; filling the first trench with a first dielectric material to form a first isolation structure to isolate the first and second transistors from each other; removing the second CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a second trench extending into the semiconductor substrate; and filling the second trench with a second dielectric material having a dielectric composition different from that of the first dielectric material to form a second isolation structure to isolated the third and fourth transistors from each other.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

Abstract: A method of manufacturing a Schottky barrier diode includes: forming a first well region and a second well region adjacent to the first well region in a substrate; depositing a first dielectric layer over the first well region and the second well region; performing a first patterning operation on the first dielectric layer to cause the first dielectric layer to include a stepped shape; performing a second patterning operation on the first dielectric layer to form a gate dielectric layer of a first transistor device in the second well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate and an oxidation region formed on the semiconductive substrate. The oxidation region includes a stage with a first width along a horizontal direction. The semiconductor structure further includes a fin formed on a top surface of the stage. A method for forming the semiconductor structure is also provided.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.