Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device may include a first device on a first portion of a substrate, a second device on a second portion of the substrate, and a third device on a third portion of the substrate. The third device may include an oxide layer that is formed from an oxide layer that is a sacrificial oxide layer for the first device and the second device. The third device may include a gate provided on the oxide layer, a set of spacers provided on opposite sides of the gate, and a source region provided in the third portion of the substrate on one side of the gate. The third device may include a drain region provided in the third portion of the substrate on another side of the gate, and a protective oxide layer provided on a portion of the gate and a portion of the drain region.

Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: In general, the subject matter described in the specification can be embodied in methods, systems and program products for a verified participant database system that verifies information on potential participants for surveys and promotions that require numerous participants with certain characteristics. Among other features, the verified participant database system aggregates and preferably verifies information, for example, the demographic and purchasing information, of potential participants by receiving permission to obtain information from third-party sources.

Abstract: A cosmetic container has a container body, an upper casing, and a lower casing. The container body has an upper housing and a lower housing being rotatable relative to each other. The upper casing is detachably and orientationally sleeved on the upper housing to rotate the upper housing with the upper casing. The lower casing is detachably and orientationally sleeved on the lower housing to rotate the lower housing with the lower casing. Because the upper casing and the lower casing are orientationally mounted around the upper housing and the lower housing, respectively, variety and variability in appearance of the cosmetic container can be provided without affecting its functional operation. Marks, textures, and patterns on an external surface of the container body can be protected.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: An array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer covering the gate; a first semiconductor layer and a second semiconductor layer that are provided on the first insulating layer, a channel corresponding to the gate being provided in the first semiconductor layer and second semiconductor layer, the second semiconductor layer including a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are stacked, both the first metal oxide semiconductor layer and the second metal oxide semiconductor layer being disconnected at the channel, and the oxygen vacancy concentration of the second metal oxide semiconductor layer being less than the oxygen vacancy concentration of the first metal oxide semiconductor layer; and a source and a drain that are provided on the second semiconductor layer, both the source and the drain being in electrically conductive contact with the second semiconductor layer.

Abstract: A method for forming an integrated circuit includes following operations. A substrate is received. The substrate includes a first region, a second region and an isolation structure. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed on a portion of the first top surface, a top of the second top surface and the boundary. A dielectric structures is formed over the substrate. Top surfaces of the dielectric structure, the first device, the second device and the dummy structure are aligned with each other. A first metal gate is formed in the first device, and a second metal gate is formed in the second device.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: In general, the subject matter described in the specification can be embodied in methods, systems and program products for an improved review system with location-verified reviews. The system verifies a user’s location using one or more available sources, such as geographic location by global positioning system (GPS), cellular localization systems, or wireless local area network (WLAN). The user confirms the business or attraction at the current geographic location that the user would like to review. The system then accepts a review of the business or attraction at the current geographic location. The review is indexed for retrieval. Preferably, the system includes a delay before indexing a review, wherein the management of the business or attraction is notified of the review so that it can respond to any complaints in the review before it is made available for retrieval.

Abstract: An electronic detection interface for testing micro photoelectric chips or micro semiconductor chips comprises a substrate structure and a plurality of detection units in array, responsive to the micro photoelectric chips or the micro semiconductor chips. The substrate structure includes a circuit film, which comprises a plurality of circuit units in array. The detection units are disposed on a surface of the substrate structure, and are corresponded to the circuit units in a respect manner. Each of the detection units includes at least one resilient conductive pillar, which is electrically connected to each of the circuit units through a conductive pad. Each of the resilient conductive pillars is a conductive photoresist.

Abstract: A device includes an integrated circuit, a first seal ring, a second seal ring, and a dielectric layer. The first seal ring surrounds the integrated circuit and includes a plurality of first seal portions separated from each other by a plurality of first gaps. The second seal ring surrounds the integrated circuit, between the integrated circuit and the first seal ring and includes a plurality of second seal portions separated from each other by a plurality of second gaps. The dielectric layer surrounds the first and second seal rings and includes a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively. A connection line of one of the first filling portions and one of the second filling portions closest to said one of the first filling portions is not parallel to edges of the integrated circuit.

Abstract: Disclosed herein is an information processing apparatus including a processor and a memory. The processor references a list indicative of correspondence between a genre of products in electronic commerce and tags to be attached to the products, thereby determining at least one tag not corresponding to the genre. The processor performs a process of training a machine learning model including at least a classifier that determines an output value of each of the at least one tag related to the products on the basis of an embedded expression in product information on the products, the training process being performed on the basis of a loss function of the at least one output value excluding the output value related to each of the at least one tag not corresponding to the genre of the products.

Abstract: An electronic device includes a substrate, plural varactors, a memory element, a driving unit and plural antenna elements. Each varactor is defined with a capacitor-voltage characteristic curve. The memory element is defined with one or more lookup tables for recording the capacitance values and varactor voltage values of the capacitor-voltage characteristic curve. The driving unit outputs plural voltage signals respectively to the varactors, and each voltage signal respectively provided with one varactor voltage value. Each antenna element is provided with various phase values in response to the capacitance values of the corresponding varactor. A selective one of the varactor voltage values in response to the required capacitance value of the corresponding varactor is found out from the lookup table(s) and delivered by the driving unit.

Abstract: A substrate structure includes a substrate and plural conductive structures. The substrate has a substrate body, plural through holes penetrating the substrate body, and two conductive patterns formed on two opposite surfaces of the substrate body respectively. The substrate body is defined with two openings, a hole wall, and a surface roughness along the hole wall. The conductive structures are respectively oriented at the through holes. Each conductive structure is defined with two larger-diameter caps, and a small-diameter segment linking the two larger-diameter caps. In each conductive structure, the two larger-diameter caps are respectively located at the two openings and electrically connected the two conductive patterns, and the surface roughness of the small-diameter segment is less than the surface roughness of the hole wall of a corresponding one of the through holes.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.