Abstract: A lock mechanism is configured to be arranged on one of a first object and a second object movable relative to each other. The lock mechanism includes a driving device and a locking member. The locking member is configured to be driven by the driving device to move between a first position and a second position in a non-rotatable manner. When the locking member is located at the first position, the locking member is configured to lock the other one of the first object and the second object. When the locking member is located at the second position, the locking member is does not lock the other one of the first object and the second object.

Abstract: An angular position sensing device for detecting angular position of a rotor of a motor includes a first resolver that includes an annular rotor, an annular stator, a plurality of excitation coils and four induction coils. The annular stator has a stator annular body, and a plurality of stator magnetic poles. One of the annular rotor and the annular stator surrounds the other one of the annular rotor and the annular stator. The excitation coils are respectively wound on the stator magnetic poles of the annular stator. The induction coils are respectively wound on four of the stator magnetic poles.

Abstract: An optical sensing apparatus including a light sensor, a plurality of light-emitting devices, and a controller is provided. The light sensor is disposed on a substrate. The light sensor senses a light reflection signal in a sensing area of the optical sensing apparatus. The light-emitting devices are disposed on the substrate and around the light sensor. The light-emitting devices provide an optical signal to be transmitted into the human tissue. Then, the optical signal is reflected by the human tissue to generate the light reflection signal. The controller determines whether the position of the human tissue has been changed in the sensing area. The controller drives at least one light-emitting device of the light-emitting devices and adjusts the light intensity thereof to provide the appropriate optical signal. Besides, a measuring method of the optical sensing apparatus is proposed.

Abstract: A physiological signal measuring method and a physiological signal measuring device are provided. The physiological signal measuring method includes the following steps: A first inputting signal having a first frequency, a second inputting signal having a second frequency and a third inputting signal having a third frequency are respectively inputted to at least two electrode sheets attached on a skin. A first impedance value corresponding to the first inputting signal, a second impedance value corresponding to the second inputting signal and a third impedance value corresponding to the third inputting signal are respectively measured. An interference impedance between the electrode sheets and the skin is obtained according to the first frequency, the second frequency, the third frequency, the first impedance value, the second impedance value and the third impedance value. A measured physiological signal is corrected according to the interference impedance to obtain a corrected physiological signal.

Abstract: A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.

Abstract: A detecting apparatus and a detecting method for physiological information are provided. The detecting apparatus includes a first optical signal provider configured to provide an organism with a first optical signal, a signal receiver configured to receive the first physiological signal, and a processor. The first optical signal, after interacting with the organism, turns into a first physiological signal. The processor is configured to calculate a plurality of physiological information values of the organism according to the first physiological signal; determine whether or not any of the physiological information values is abnormal; and replace the abnormal physiological information value with a physiological information reliable value when there is the abnormal physiological information value.

Abstract: A physiological signal measuring method and a physiological signal measuring device are provided. The physiological signal measuring method includes the following steps: A first inputting signal having a first frequency, a second inputting signal having a second frequency and a third inputting signal having a third frequency are respectively inputted to at least two electrode sheets attached on a skin. A first impedance value corresponding to the first inputting signal, a second impedance value corresponding to the second inputting signal and a third impedance value corresponding to the third inputting signal are respectively measured. An interference impedance between the electrode sheets and the skin is obtained according to the first frequency, the second frequency, the third frequency, the first impedance value, the second impedance value and the third impedance value. A measured physiological signal is corrected according to the interference impedance to obtain a corrected physiological signal.

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract: An optical sensing apparatus including a light sensor, a plurality of light-emitting devices, and a controller is provided. The light sensor is disposed on a substrate. The light sensor senses a light reflection signal in a sensing area of the optical sensing apparatus. The light-emitting devices are disposed on the substrate and around the light sensor. The light-emitting devices provide an optical signal to be transmitted into the human tissue. Then, the optical signal is reflected by the human tissue to generate the light reflection signal. The controller determines whether the position of the human tissue has been changed in the sensing area. The controller drives at least one light-emitting device of the light-emitting devices and adjusts the light intensity thereof to provide the appropriate optical signal. Besides, a measuring method of the optical sensing apparatus is proposed.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract: A gas detecting system, device and method use a variable pulse voltage waveform to increase the temperature of a detecting unit of the gas detecting system so it reacts with gas molecules from a particular space, and outputs a sensing signal. A processing unit of the gas detecting system then performs calculations on the sensing signal, such that an analysis unit may determine the presence of a target gas in the particular space, and further the composition and concentration of the target gas within the particular space, thus providing a detection that is accurate, rapid and convenient.

Abstract: The present disclosure relates to new DNA-directed alkylating agents and water-soluble N-mustard agents with improved chemical stability and anti-tumor therapeutic efficacy.

Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Abstract: A static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.

Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.

Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.