Abstract: A detection method for detecting a QRS wave is disclosed. An electrocardiogram (ECG) signal is provided. The ECG signal is enhanced to generate a processed signal. A first crest of the processed signal is determined. Each crest following the first crest is defined as a second crest. The level of each second crest is higher than a first threshold value. The result of defining the second crest is utilized to determine whether the QRS wave has occurred and approached a first crest.

Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.

Abstract: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract: An energy storage device package is provided. The energy storage device package includes a bottom cover and a top cover connected to form a hollow chamber to accumulate an electrolyte, a first electrode and a second electrode formed on the top cover and which stretch from the top cover to the hollow chamber to contact the electrolyte, and a safety valve. The first electrode includes an opening and an exhaust channel that extends between the hollow chamber and the opening. When a gas pressure in the hollow chamber is smaller than or equal to a threshold value, the safety valve in the first electrode blocks the exhaust channel. When the gas pressure is larger than the threshold value, the gas pushes to open the safety valve and flows out from the hollow chamber through the exhaust channel and the opening.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract: A method for manufacturing light-emitting diode devices. Multiple metal frames are provided. The metal frames are adjacent to each other and are arranged on a same plane. Each metal frame includes a first connection pin and a second connection pin. A light-emitting diode chip is disposed on and electrically connected to each metal frame. The metal frames are respectively bent, enabling the adjacent metal frames to separate from each other. A moldboard formed with a plurality of mold cavities is provided. The bent metal frames are respectively disposed in the mold cavities, locating each light-emitting diode chip in each mold cavity. The mold cavities are respectively filled with package gel. The package gel filled in each mold cavity covers each light-emitting diode chip. The package gel is solidified. The mold cavities are separated from the package gel. The metal frames are separated from each other, forming the light-emitting diode devices.

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract: A light-emitting diode (LED) lighting device includes a base, which has an end forming a head portion and an opposite end forming a lighting body. The lighting body includes a support plate having an end coupled to the base and supporting multiple thermal conduction bars. Each thermal conduction bar carries one or more lighting assemblies. The lighting assembly includes a bracket and a light source unit. The light source unit is set to project light of uniform brightness in a given direction. The grating like three-dimensional lighting device features light weight and excellent air ventilation and heat dissipation and allows an LED lighting device to be adopted in an existing fixture.

Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

Abstract: A method of correcting and detecting errors in a sector of data stored in a DVD format is provided. The method includes: calculating an initial error detection value for data within the sector, performing an error correction operation on the data within the sector and determining an updated, intermediate error detection value responsive to the error correction operation, using a target error detection value and one of the initial error detection value and the intermediate error detection value to determine that the sector doesn't include errors, processing an outer code to provide a set of error patterns and error locations, and determining if any of the error locations are for data within the sector and not correcting data corresponding to the error locations within the sector.

Abstract: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Abstract: A back light plate includes a plurality of light bars of high light transmittance. The light bars are juxtaposed to form a flat plate like or a grating like light emission structure. Each light bar has opposite ends to which light sources, such as light-emitting diodes, are mounted. Light emitting from the light sources can transmit through the light bar to form a uniform luminous cylinder and thereby constituting a wide span of backlighting. This arrangement saves the number of light-emitting diodes used, makes the manufacturing easy, and provides a simple and convenient-to-carry-out manufacturing process as compared to the conventional manufacturing processes of large-sized thin back light plate, so as to lead to a significant reduction of manufacturing costs.

Abstract: The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.

Abstract: An illumination lamp includes an electric connection portion, a heat dissipating casing, a printed circuit board, light emitting diodes and a transparent cover. The heat dissipating casing is installed onto the electric connection portion and includes abuse wall and a surrounding wall. The base wall has an arc camber protruded from the periphery of the base wall towards the center of the base wall and away from the electric connection portion. The surrounding wall is extended from the periphery of the base wall. The printed circuit board includes a center hole and a groove, and is attached onto the base wall. The light emitting diodes are installed separately on the printed circuit board. The transparent cover is covered onto a side of the heat dissipating casing. Since the light emitting diodes are installed along the arc camber, the illumination range is expanded, and the illumination uniformity is enhanced.

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.