Patents by Inventor Teng-Chun Tsai

Teng-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444028
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 11398381
    Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Teng-Chun Tsai
  • Patent number: 11389928
    Abstract: A method is provided and includes: measuring a surface profile of a polishing pad; obtaining a reference profile of the polishing pad; comparing the surface profile of the polishing pad with the reference profile to generate a difference result; determining a conditioning parameter value according to the difference result; and conditioning the polishing pad using the conditioning parameter value.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shen-Nan Lee, Te-Chien Hou, Teng-Chun Tsai, Chung-Wei Hsu, Chen-Hao Wu
  • Patent number: 11387138
    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Shuen-Shin Liang, Keng-Chu Lin, Teng-Chun Tsai
  • Publication number: 20220195246
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 23, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao
  • Publication number: 20220190137
    Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
  • Patent number: 11312882
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 11267987
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao
  • Patent number: 11264485
    Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
  • Patent number: 11227788
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Publication number: 20210384322
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiang LIN, Teng-Chun TSAI, Huang-Lin CHAO, Akira MINEJI
  • Patent number: 11193043
    Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 7, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., Uwiz Technology Co., Ltd.
    Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Song-Yuan Chang, Teng-Chun Tsai
  • Publication number: 20210375667
    Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
    Type: Application
    Filed: July 12, 2021
    Publication date: December 2, 2021
    Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
  • Patent number: 11164956
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiang Lin, Teng-Chun Tsai, Akira Mineji, Huang-Lin Chao
  • Patent number: 11152267
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Publication number: 20210288161
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 16, 2021
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210287904
    Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei SU, Fu-Ting YEN, Ting-Ting CHEN, Teng-Chun TSAI
  • Patent number: 11120995
    Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei Hsu, Yu-Chung Su, Chen-Hao Wu, Shen-Nan Lee, Tsung-Ling Tsai, Teng-Chun Tsai
  • Publication number: 20210280473
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Application
    Filed: May 7, 2021
    Publication date: September 9, 2021
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Publication number: 20210265222
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO