Patents by Inventor Teng-Chun Tsai

Teng-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031391
    Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shen-Nan Lee, Kuo-Yin Lin, Pin-Chuan Su, Teng-Chun Tsai
  • Patent number: 11024504
    Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Ting-Ting Chen, Teng-Chun Tsai
  • Patent number: 11018246
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11011385
    Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
  • Patent number: 11004794
    Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Ling Tsai, Shen-Nan Lee, Mrunal A. Khaderbad, Chung-Wei Hsu, Chen-Hao Wu, Teng-Chun Tsai
  • Patent number: 11004691
    Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hao Wu, Shen-Nan Lee, Chung-Wei Hsu, Tsung-Ling Tsai, Teng-Chun Tsai
  • Publication number: 20210118748
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Publication number: 20210104431
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 8, 2021
    Inventors: Mrunal A. Khaderbad, Yasutoshi Okuno, Sung-Li Wang, Pang-Yen Tsai, Shen-Nan Lee, Teng-Chun Tsai
  • Publication number: 20210098266
    Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.
    Type: Application
    Filed: August 12, 2020
    Publication date: April 1, 2021
    Inventors: An-Hsuan Lee, Chun-Hung Liao, Chen-Hao Wu, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20210098283
    Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.
    Type: Application
    Filed: November 20, 2020
    Publication date: April 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shen-Nan LEE, Teng-Chun TSAI, Chen-Hao WU, Chu-An LEE, Chun-Hung LIAO, Tsung-Ling TSAI
  • Patent number: 10964542
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Patent number: 10964549
    Abstract: A wafer is polished by performing a chemical reaction to change a property of a first portion of a material layer on the wafer using a first chemical substance. A first rinse is performed to remove the first chemical substance and retard the chemical reaction. A mechanical polishing process is then performed to remove the first portion of the material layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shen-Nan Lee, Teng-Chun Tsai, Chu-An Lee, Chen-Hao Wu, Chun-Hung Liao, Huang-Lin Chao
  • Publication number: 20210090944
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 25, 2021
    Inventors: Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Publication number: 20210057543
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang LIN, Teng-Chun TSAI, Akira MINEJI, Huang-Lin CHAO
  • Publication number: 20210050430
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
  • Patent number: 10920105
    Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Hsuan Lee, Shen-Nan Lee, Chen-Hao Wu, Chun-Hung Liao, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20200407594
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 10879117
    Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia Yeo, Teng-Chun Tsai, Yasutoshi Okuno
  • Patent number: 10868180
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10861752
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu