Patents by Inventor Teng-Hao Yeh

Teng-Hao Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607661
    Abstract: A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 31, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Yi-Ching Liu
  • Publication number: 20200098774
    Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 10593697
    Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh, Yu-Wei Jiang, Kuo-Pin Chang
  • Patent number: 10566348
    Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 10535673
    Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 14, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Publication number: 20190371804
    Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Applicant: Macronix International Co., Ltd.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Patent number: 10490498
    Abstract: A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: November 26, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Min-Feng Hung, Chih-Wei Hu
  • Patent number: 10388720
    Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Teng-Hao Yeh
  • Patent number: 10340222
    Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 2, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Publication number: 20190122983
    Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Publication number: 20180301407
    Abstract: A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: Teng-Hao Yeh, Min-Feng Hung, Chih-Wei Hu
  • Patent number: 10068914
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 4, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Teng-Hao Yeh
  • Patent number: 10014306
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 3, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Patent number: 9947665
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 17, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Publication number: 20170323896
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.
    Type: Application
    Filed: October 11, 2016
    Publication date: November 9, 2017
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Patent number: 9761319
    Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 12, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo-Pin Chang, Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 9748264
    Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a memory structure including first memory structure clusters and second memory structure clusters, isolation trenches, and common source trenches. The conductive layers and the insulating layers are interlaced and stacked on the substrate. Each first memory structure cluster include first memory structures and each first memory structure cluster include second memory structures. The first and second memory structures penetrate the conductive layers and the insulating layers. Each isolation trench is formed between a first memory structure cluster and a second memory structure cluster. The isolation trenches span horizontally on the substrate in a discontinuous manner separated by gaps. Common source trenches are formed on the substrate that run substantially parallel with the isolation trenches.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 29, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu Wei Jiang, Teng Hao Yeh
  • Patent number: 9741569
    Abstract: A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: August 22, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Patent number: 9721668
    Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 1, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Kuo-Pin Chang
  • Patent number: 9716137
    Abstract: An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: July 25, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh