Abstract: A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stack structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stack structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stack structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

Abstract: Roughly described, the invention involves a device including a memory chip having a memory array, bit lines in communication with data carrying nodes of the memory array, and word lines in communication with certain gate control nodes of the memory array. The memory chip has bonding pads formed on an interconnect surface at respective memory chip interconnect locations. Each of the bit lines and each of the word lines of the memory array includes a respective landing pad in a conductive layer of the chip, and these landing pads connected via redistribution conductors to respective ones of the set of memory chip bonding pads. The redistribution conductors for the bit lines have a positive average lateral signal travel distance which is less than that of the redistribution conductors for the word lines.

Abstract: A 3D memory device includes a multi-layers stacking structure, a memory layer, a channel layer, and a switching element. The multi-layers stacking structure includes a plurality of conductive layers, a plurality of insulating layers, and an opening. The insulating layer and the conductive layer are stacked along a stacking direction in a staggered manner, and the opening passes through the conductive layer. The memory layer is disposed in the opening and at least partially overlaps the conductive layers. The channel layer is disposed in the opening and overlaps the memory layer. The switching element includes a channel plug disposed over the multi-layers stacking structure and electrically connecting to the channel layer, a first gate dielectric layer surrounding the channel plug, and at gate surrounding the gate dielectric layer.

Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

Abstract: A 3D memory array device includes blocks, bit lines, word lines, source lines (SL), complementary metal oxide semiconductors (COMS), and SL sensing amplifiers (SA). Each block includes NAND strings, and each memory cell in the NAND strings stores one or more weights. The bit lines are respectively coupled as signal inputs to string select lines in all blocks. The word lines are respectively coupled to the memory cells, and the word lines in the same layer are as a convolution layer to perform a convolution operation on the inputted signal. Different SL are coupled to all ground select lines in different blocks to independently collect a total current of the NAND strings in each block. The CMOS are disposed under the blocks and coupled to each source line for transferring the total current to each SL SA, and a multiply-accumulate result of each block is outputted via each SL SA.

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

Abstract: A semiconductor structure includes a plurality of stacks, a plurality of active pillars, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active pillars are disposed in the trenches and separated from each other in each of the trenches. Each of the active pillars comprises two n-type heavily doped portions at two sides thereof. Each of the two n-type heavily doped portions extends in a substantially vertical direction. Each of the two n-type heavily doped portions connects corresponding two stacks of the plurality of stack. The insulating material is located in remaining spaces of the trenches between the active pillars. The insulating material is a silicon glass comprising an element which is applicable as a n-type dopant.

Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.

Abstract: A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.

Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.

Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.

Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.