Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.

Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip.

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.

Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a memory structure including first memory structure clusters and second memory structure clusters, isolation trenches, and common source trenches. The conductive layers and the insulating layers are interlaced and stacked on the substrate. Each first memory structure cluster include first memory structures and each first memory structure cluster include second memory structures. The first and second memory structures penetrate the conductive layers and the insulating layers. Each isolation trench is formed between a first memory structure cluster and a second memory structure cluster. The isolation trenches span horizontally on the substrate in a discontinuous manner separated by gaps. Common source trenches are formed on the substrate that run substantially parallel with the isolation trenches.

Abstract: A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

Abstract: An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.

Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.

Abstract: A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines disposed on the first conductive lines, a top metal plate disposed on the second conductive lines, and at least one strapping structure. The second conductive lines and the first conductive lines extend on different directions. The at least one strapping structure is configured for the first conductive lines and correspondingly disposed on at least one dummy region of the 3D array. Each strapping structure includes a connecting structure and a jumping line. The jumping line is disposed on and coupled to the connecting structure, and coupled to the top metal plate. The jumping line and the second conductive lines extend on the same direction.

Abstract: A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.

Abstract: A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract: A 3D memory structure and a method for manufactured the same are provided. The 3D memory structure comprises a plurality of strings, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of third conductive lines. The strings are disposed in parallel. The first conductive lines are disposed over the strings. Center regions of the first conductive lines are disposed perpendicular to the strings. The second conductive lines are disposed over the first conductive lines. The second conductive lines connect end regions of half of the first conductive lines. The third conductive lines are disposed over the second conductive lines. The third conductive lines connect end regions of the other half of the first conductive lines.

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.